PIC18F46K80-I/ML Microchip Technology Inc., PIC18F46K80-I/ML Datasheet - Page 210
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PIC18F46K80-I/ML
Manufacturer Part Number
PIC18F46K80-I/ML
Description
44 QFN 8X8X0.9MM TUBE, ECAN, 64KB FLASH, 4KB RAM, 16 MIPS, 12-BIT ADC, CTMU
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F46K80-IPT.pdf
(628 pages)
Specifications of PIC18F46K80-I/ML
A/d Inputs
11-Channel, 12-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
1K Bytes
Input Output
35
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin QFN
Programmable Memory
64K Bytes
Ram Size
3.6K Bytes
Speed
64 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 3-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC18F66K80 FAMILY
REGISTER 12-4:
TABLE 12-1:
DS39977C-page 210
MDCARH MDCHODIS
MDCARL
MDCON
MDSRC
PMD2
Legend: — = unimplemented, read as ‘ 0 ’. Shaded cells are not used in the Data Signal Modulator mode.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note 1:
MDCLODIS
Name
R/W-0
Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
MDCLODIS
MDSODIS
MDEN
Bit 7
MDCLODIS: Modulator Low Carrier Output Disable bit
1 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register)
0 = Output signal driving the peripheral output pin (selected by MDCL<3:0> of the MDCARL register)
MDCLPOL: Modulator Low Carrier Polarity Select bit
1 = Selected low carrier signal is inverted
0 = Selected low carrier signal is not inverted
MDCLSYNC: Modulator Low Carrier Synchronization Enable bit
1 = Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high
0 = Modulator output is not synchronized to the low time carrier signal
Unimplemented: Read as ‘ 0 ’
MDCL<3:0> Modulator Data High Carrier Selection bits
1111 - 1001 = Reserved
1000 = CCP5 output (PWM Output mode only)
0111 = CCP4 output (PWM Output mode only)
0110 = CCP3 output (PWM Output mode only)
0101 = CCP2 output (PWM Output mode only)
0100 = ECCP1 output (PWM Output mode only)
0011 = Reference clock module signal
0010 = MDCIN2 port pin
0001 = MDCIN1 port pin
0000 = V
MDCLPOL
—
SUMMARY OF REGISTERS ASSOCIATED WITH DATA SIGNAL MODULATOR MOD
R/W-x
is disabled
is enabled
time carrier
MDCARL: MODULATION LOW CARRIER CONTROL REGISTER
SS
MDCHPOL
MDCLPOL
MDOE
Bit 6
W = Writable bit
‘1’ = Bit is set
MDCLSYNC
—
—
R/W-x
MDCHSYNC
MDCLSYNC
MDSLR
Bit 5
—
—
U-0
Preliminary
—
MDOPOL
Bit 4
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
—
—
—
—
MDCL3
R/W-x
(1)
MDSRC3
MODMD
MDCH3
MDCL3
MDO
Bit 3
(1)
MDCL2
R/W-x
ECANMD
MDSRC2
MDCH2
MDCL2
(1)
Bit 2
—
(1)
2011 Microchip Technology Inc.
x = Bit is unknown
MDCL1
R/W-x
CMP2MD
MDSRC1
MDCH1
MDCL1
Bit 1
—
(1)
MDCL0
CMP1MD
MDSRC0
MDCH0
MDCL0
R/W-x
MDBIT
Bit 0
bit 0
(1)
E
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