MAX8660BETL+T Maxim Integrated Products, MAX8660BETL+T Datasheet - Page 35

• Manufacturer Part Number: MAX8660BETL+T
• Description: Other Power Management Low-IQ PMIC w/Dynamic V Mgt
• Manufacturer: Maxim Integrated Products

Specifications of MAX8660BETL+T

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issuing
a START condition. A START condition is a high-to-low
transition on SDA with SCL high. A STOP condition is a
low-to-high transition on SDA, while SCL is high (Figure 8).
A START condition from the master signals the begin-
ning of a transmission to the MAX8660/MAX8661. The
master terminates transmission by issuing a not-
acknowledge followed by a STOP condition (see the
Acknowledge Bit section for more information). The
STOP condition frees the bus. To issue a series of com-
mands to the slave, the master may issue repeated
start (Sr) commands instead of a stop command in
order to maintain control of the bus. In general, a
repeated start command is functionally equivalent to a
regular start command.
When a STOP condition or incorrect address is detected,
the MAX8660/MAX8661 internally disconnect SCL from
the serial interface until the next START condition, mini-
mizing digital noise and feedthrough.
Figure 10. Slave Address Byte
Figure 9. Acknowledge Bits
Figure 8. START and STOP Conditions
SDA
SCL
SDA
SCL
S
Voltage Management for Mobile Applications
High-Efficiency, Low-I
S
t
HD;STA
______________________________________________________________________________________
SDA
SCL
0
1
START and STOP Conditions
Sr
S
t
SU;STA
1
2
t
HD;STA
0 (GND)
SRAD
1 (IN)
1
1
3
0b 0110 1000
0b 0110 1010
P
SLAVE ADDRESS (WRITE)
BINARY
2
t
SU;STO
0
4
HEXADECIMAL
Both the master and the MAX8660/MAX8661 (slave)
generate acknowledge bits when receiving data. The
acknowledge bit is the last bit of each 9-bit data packet.
To generate an acknowledge (A), the receiving device
must pull SDA low before the rising edge of the acknowl-
edge-related clock pulse (ninth pulse) and keep it low
during the high period of the clock pulse (Figure 9). To
generate a not acknowledge (A), the receiving device
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse and leaves it high
during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a sys-
tem fault has occurred. In the event of an unsuccessful
data transfer, the bus master should reattempt commu-
nication at a later time.
A bus master initiates communication with a slave
device (MAX8660/MAX8661) by issuing a START condi-
tion followed by the slave address. As shown in Figure
10, the slave address byte consists of 7 address bits
and a read/write bit (R/W). After receiving the proper
address, the MAX8660/MAX8661 issue an acknowledge
by pulling SDA low during the ninth clock cycle. Note
that the R/W bit is always zero since the MAX8660/
MAX8661 are write only.
The Marvell PXA3xx processor supports 0x68 (SRAD =
GND) as the I
0x6A
0x68
1
5
Q
, PMICs with Dynamic
NOT ACKNOWLEDGE
t
SU;DAT
8
0
6
2
C slave address.
(WRITE ONLY)
9
R / W = 0
SRAD
ACKNOWLEDGE
7
t
HD;DAT
0
8
Acknowledge Bit
Slave Address
A
9
ACKNOWLEDGE
35