CAT1163J-42 Catalyst / ON Semiconductor, CAT1163J-42 Datasheet - Page 10

• Manufacturer Part Number: CAT1163J-42
• Description: Supervisory Circuits 16K I2C Memory w/WDT
• Manufacturer: Catalyst / ON Semiconductor

Specifications of CAT1163J-42

• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Output Type: Active High, Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2.7 V
• Supply Current (typ): 3000 uA
• Maximum Power Dissipation: 1000 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Minimum Operating Temperature: 0 C
• Power Fail Detection: No
• Undervoltage Threshold: 4.25 V
• Overvoltage Threshold: 4.5 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CAT1163
Selective/Random Read
Selective/Random READ operations allow the
Master device to select at random any memory
location for a READ operation. The Master device
first performs a ‘dummy’ write operation by sending
the START condition, slave address and byte
addresses of the location it wishes to read. After the
CAT1163 acknowledges, the Master device sends
the START condition and the slave address again,
this time with the R/W ¯ ¯ bit set to one. The CAT1163
then responds with its acknowledge and sends the
8-bit byte requested. The master device does not
send an acknowledge but will generate a STOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective
READ operations. After the CAT1163 sends the
inital 8-bit byte requested, the Master will responds
with an acknowledge which tells the device it
requires more data. The CAT1163 will continue to
output an 8-bit byte for each acknowledge, thus
sending the STOP condition.
The data being transmitted from the CAT1163 is
outputted sequentially with data from address N
followed by data from address N+1. The READ
operation address counter increments all of the
CAT1163 address bits so that the entire memory
Figure 10. Selective Read Timing
Figure 11. Sequential Read Timing
Doc. No. MD-3003 Rev. I
BUS ACTIVITY:
SDA LINE
MASTER
BUS ACTIVITY:
SDA LINE
MASTER
ADDRESS
SLAVE
S
S
A
R
T
T
A
C
K
ADDRESS
SLAVE
DATA n
A
C
K
ADDRESS (n)
A
C
K
BYTE
DATA n+1
10
array can be read during one operation. If more than E
(where E=2047 for the CAT1163) bytes are read out,
the counter will ‘wrap around’ and continue to clock out
data bytes.
Manual Reset Operation
The CAT116x RESET or RESET
as a manual reset input.
Only the “active” edge of the manual reset input is
internally sensed. The positive edge is sensed if
RESET is used as a manual reset input and the
negative edge is sensed if RESET
reset input.
An internal counter starts a 200ms count. During this
time, the complementary reset output will be kept in the
active state. If the manual reset input is forced active for
more than 200ms, the complementary reset output will
switch back to the non active state after the 200ms
expired, regardless for how long the manual reset input
is forced active.
The embedded EEPROM is disabled as long as a reset
condition is maintained on any RESET pin. If the
external forced RESET/RESET
controlled time-out period, t
respond with an acknowledge for any access as long as
the manual reset input is active.
A
C
K
S
A
R
T
S
T
C
A
K
ADDRESS
SLAVE
DATA n+2
C
A
K
A
C
K
¯¯¯¯¯¯ is longer than internal
¯¯¯¯¯¯ pin can also be used
DATA n
¯¯¯¯¯¯ is used as a manual
Characteristics subject to change without notice
PURST
DATA n+x
, the memory will not
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