CAT1163PI-30 Catalyst / ON Semiconductor, CAT1163PI-30 Datasheet - Page 5

• Manufacturer Part Number: CAT1163PI-30
• Description: Supervisory Circuits 16K I2C Memory w/WDT
• Manufacturer: Catalyst / ON Semiconductor

Specifications of CAT1163PI-30

• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Output Type: Active High, Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No Backup
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2.7 V
• Supply Current (typ): 3000 uA
• Maximum Power Dissipation: 1000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-8
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Undervoltage Threshold: 3 V
• Overvoltage Threshold: 3.15 V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIN DESCRIPTION
WDI: WATCHDOG INPUT
If there is no transition on the WDI for more than 1.6
seconds, the watchdog timer times out.
WP: WRITE PROTECT
If the pin is tied to V
becomes Write Protected (READ only). When the pin
is tied to GND or left floating normal read/write
operations are allowed to the device.
RESET/RESET
These are open drain pins and can be used as reset
trigger inputs. By forcing a reset condition on the pins
the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull-
down resistor, and the RESET
through a pull-up resistor.
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
SCL: SERIAL CLOCK
Serial clock input.
DEVICE OPERATION
Reset Controller Description
The CAT1163 precision RESET controller ensures
correct system operation during brownout and power
up/down conditions. It is configured with open drain
Figure 1. RESET Output Timing
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
¯¯¯¯¯¯
RESE T
RESE T
V
CC
V
RVALID
: RESET I/O
V
TH
¯¯¯¯¯¯ pin must be connected
CC
the entire memory array
t
PURST
t
GLITCH
t
5
RPD
RESET outputs. During power-up, the RESET outputs
remain active until V
will continue driving the outputs for approximately
200ms (t
timeout interval, the device will cease to drive the
reset outputs. At this point the reset outputs will be
pulled up or down by their respective pull up/down
resistors. During power-down, the RESET outputs will
be active when V
outputs will be valid so long as V
The RESET pins are I/Os; therefore, the CAT1163
can act as a signal conditioning circuit for an
externally applied manual reset. The inputs are edge
triggered; that is, the RESET input in the CAT1163 will
initiate a reset timeout after detecting a low to high
transition and the RESET
initiate a reset timeout after detecting a high to low
transition.
Watchdog Timer
The Watchdog Timer provides an independent
protection for microcontrollers. During a system
failure, the CAT1163 will respond with a reset signal
after a time-out interval of 1.6 seconds for a lack of
activity. The CAT1163 is designed with the Watchdog
Timer feature on the WDI input. If the microcontroller
does not toggle the WDI input pin within 1.6 seconds,
the Watchdog Timer times out. This will generate a
reset condition on reset outputs. The Watchdog Timer
is cleared by any transition on WDI.
As long as the reset signal is asserted, the Watchdog
Timer will not count and will stay cleared.
PURST
) after reaching V
t
PURST
¯¯¯¯¯¯ input in the CAT1163 will
CC
CC
falls below V
reaches the V
CC
t
RPD
TH
is >1.0V (V
. After the t
TH
TH
Doc. No. MD-3003 Rev. I
. The RESET
threshold and
CAT1163
RVALID
¯¯¯¯¯¯
PURST
).