SI5100-H-GL Silicon Laboratories Inc, SI5100-H-GL Datasheet
SI5100-H-GL
Specifications of SI5100-H-GL
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SI5100-H-GL Summary of contents
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... DSPLL technology to provide superior jitter performance while reducing design complexity by eliminating external loop filter components. To simplify BER optimization in long-haul applications, programmable slicing and sample phase adjustment are supported. The Si5100 operates from a single 1.8 V supply over the industrial temperature range (– °C). Functional Block Diagram ...
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... Si5100 2 Rev. 1.4 ...
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... T C ABLE O F ONTENTS Section 1. Si5100 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 3. Si5100 Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5. Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1. Receiver Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2. Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.3. Clock and Data Recovery (CDR 5.4. Deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.5. Voltage Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 ...
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... Si5100 1. Si5100 Detailed Block Diagram PHASEADJ SLICEMODE RXLOL LTR SLICELVL Lim iting CDR RXDIN Amp LOSLVL LOS RXAMPMON FIFOERR FIFORST TXSQLCH TXDOUT TXCLKDSBL TXCLKOUT TXLOL TXMSBSEL BWSEL[1:0] 4 LOS 1:16 DE- MUX 16:1 32:16 FIFO MUX MUX CMU REFRA TE LPTM LLBK LLBK REFSEL Rev ...
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... Table 1. Recommended Operating Conditions Parameter Ambient Temperature LVTTL Output Supply Voltage Si5100 Supply Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. V ...
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... Si5100 All Differential IOs Figure 3. Rise/Fall Time Measurement Table 2. DC Characteristics (V = 1.8 V ±5 – ° Parameter Supply Current Power Dissipation Voltage Reference (VREF) Common Mode Input Voltage (RXDIN) Differential Input Voltage Swing (RXDIN) –12 (@ Bit Error Rate Common Mode Output Voltage ...
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... V DDIO IH2 DDIO 1.8–3.3 V — OL2 DDIO V V – 0. 1.8–3.3 V OH2 DDIO DDIO R 4 OUT R 100 IN (single-ended). PP Rev. 1.4 Si5100 Typ Max Unit 650 800 mV PPD 1.2 1.275 V Ω Ω 110 130 Ω Ω –6 — mA — 0.35 V ...
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... Si5100 Table 3. AC Characteristics (RXDIN, RXDOUT, RXCLK1, RXCLK2 1.8 V ±5 – ° Parameter Symbol Input Data Rate (RXDIN) Output Clock Frequency (RXCLK1) Output Clock Frequency (RXCLK2) Duty Cycle (RXCLK1, RXCLK2) Output Rise and Fall Times (RXCLK1, RXCLK2, RXDOUT) Data Invalid Prior to RXCLK1 ...
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... F t Figure 2 CD 100 kHz–2.5 GHz 2.5–4.0 GHz f MODE16 = 1 CLKOUT MODE16 = 0 tch/tcp, Figure DSIN t DHIN f MODE16 = 1 CLKIN MODE16 = 0 tch/tcp, Figure Rev. 1.4 Si5100 Min Typ Max Unit 2.41 — 2.7 GHz — — –42 — –22 ps — –12 — dB — ...
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... Si5100 Table 5. AC Characteristics (Receiver PLL 1.8 V ± 5 – ° Parameter Jitter Tolerance 2 (RXDIN = 100 mV , PRBS31) PPD Acquisition Time Input Reference Clock Frequency (REFSEL = 1) Reference Clock Duty Cycle Reference Clock Frequency Tolerance Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the ...
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... Valid REFCLK AQ BWSEL[1: REFRATE = 1 FREQ REFRATE = 0 RC DUTY RC TOL J BWSEL[1: GEN(rms) BWSEL[1: BWSEL[1: BWSEL[1: BWSEL[1: GEN(pp) BWSEL[1: BWSEL[1: BWSEL[1: Rev. 1.4 Si5100 Min Typ Max Unit — — 12 kHz — — 50 kHz — — 120 kHz — — 200 kHz — — ...
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... Si5100 Table 7. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL I/O Supply Voltage Differential Input Voltage (LVDS Input) Differential Input Voltage (LVDS Output) Differential Input Voltage (LVTTL Input) Differential Input Voltage (LVTTL Output) Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM (2.5 GHz Pins) ESD HBM Tolerance (100 pF, 1.5 k Ω ...
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... Si5100 Typical Application Schematic FIFORST RESET 0.1 μF High-Speed RXDIN± Serial Input LVPECL Reference REFCLK Clock 16 LVDS Parallel TXDIN[15:0]± Data Input LVDS Data TXCLK16IN± Clock Input Loss-of-Signal Level Set Note* See 15. "Power Supply Filtering" on page 21. LVTTL Control Inputs Si5100 3 ...
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... The receiver signal amplitude monitoring circuit is also used in the generation of the loss-of-signal alarm (LOS). 5.2.2. Loss-of-Signal Alarm (LOS) The Si5100 can be configured to activate a loss-of- signal alarm output (LOS) when the RXDIN input amplitude drops below a programmable threshold level. OC-48/STM-16 An appropriate level of hysteresis prevents unnecessary switching on LOS ...
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... The Si5100 provides a sample phase adjustment capability that allows adjustment of the CDR sampling phase across the NRZ data period. When sample phase adjustment is enabled, the sampling instant used for data recovery can be moved over a range of approximately ± ...
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... Figure 4. Typical LOSLVL Transfer Curve, Absolute Slice Mode (SLICEMODE = RXDOUT[3:0]. 5.4.1. Serial Input to Parallel Output Relationship The Si5100 provides the capability to select the order in which the received serial data is mapped to the parallel output bus RXDOUT[15:0]. The mapping of the receive bits to the output data word is controlled by the RXMSBSEL input ...
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... SLICELVL Transfer Curve (Absolute Slice Mode -20 -40 -60 0.35 0.4 Figure 6. Typical SLICELVL Transfer Curve, Absolute Slice Mode (SLICEMODE = 0) 0.2 0.25 0.3 0.35 LOSLVL (V) LOS Assert Threshold LOS De-assert Threshold 0.45 0.5 0.55 SLICELVL (V) Rev. 1.4 Si5100 0.4 0.45 0.5 0.6 0.65 17 ...
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... Si5100 -10 -20 -30 0.25 0.3 Figure 7. Typical SLICELVL Transfer Curve, Proportional Slice Mode (SLICEMODE = -10 -20 -30 -40 0.2 0.3 Figure 8. Typical PHASEADJ Transfer Curve 18 SLICELVL Transfer Curve (Proportional Slice Mode) 0.35 0.4 0.45 0.5 0.55 0.6 SLICELVL (V) PHASEADJ Transfer Curve 0.4 0.5 0.6 PHASEADJ (Volts) Rev ...
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... The TXLOL signal is also asserted during the transmit CMU frequency calibration. Calibration is performed automatically when the Si5100 is powered on, when a valid clock signal is detected on the selected reference clock input following a period when no valid clock was present, or when the frequency of the selected reference clock is outside of the transmit CMU’ ...
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... PCB. 6.2.3. Transmit Data Squelch To prevent the transmission of corrupted data into the network, the Si5100 provides a control pin that can be used to force the high-speed serial data output TXDOUT to zero. When the TXSQLCH input is set low, the TXDOUT signal is forced to a zero state. The TXSQLCH input is ignored when the device is in line loopback mode (LLBK = 0) ...
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... When the receive CDR locks to the data input, the RXLOL signal is deasserted (driven high). 12. Reset The Si5100 is reset by holding the RESET pin low for at least 1 µ s. When RESET is asserted, the input FIFO pointers are reset and the digital control circuitry is initialized. ...
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... Si5100 50 Ω Figure 9. CML Output Driver Termination (TXCLKOUT, TXDOUT) Figure 10. Receiver Differential Input Circuitry 22 1 Ω Ω 0.1 μ Ω 0.1 μ 1.5 V 150Ω 150Ω 0.1 μF RXDIN+ RXDIN– 0.1 μF 75Ω 75Ω Rev. 1.4 VDD 50 Ω 50 Ω ...
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... In + Out + _ In ESD Figure 11. LVDS Driver Termination (RXDOUT, TXCLK16OUT) ESD In + 100 Ω ESD Figure 12. LVDS Differential Input Circuitry 6 Ω 50 Ω 1 kΩ 5 kΩ Common Mode Adjust Circuit Rev. 1.4 Si5100 Out In + ESD 23 ...
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... GND TXDIN TXDIN TXDIN TXDIN TXDIN [11]+ [11]– [9]+ [9]– [7]+ TXDIN TXDIN TXDIN TXDIN TXDIN [10]+ [10]– [8]+ [8]– [6]+ Figure 13. Si5100 Pin Configuration (Bottom View RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT [4]– [4]+ [2]– [2]+ [0]– RXDOUT RXDOUT RXDOUT RXDOUT ...
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... GND TXLOL TXCLK16 TXCLK16 TXDIN TXDIN TXDIN N IN– IN+ [1]– [1]+ TXCLK16 TXCLK16 TXDIN TXDIN TXDIN P OUT– OUT+ [0]– [0]+ Figure 14. Si5100 Pin Configuration (Transparent Top View RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT [0]– [2]+ [2]– [4]+ [4]– [6]+ RXDOUT RXDOUT RXDOUT RXDOUT RXDOUT [1]– ...
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... Si5100 17. Pin Descriptions: Si5100 Alphabetically listed by name Pin Number(s) Name M10 BWSEL1 M7 BWSEL0 F12 DLBK K3 FIFOERR M6 FIFORST B1, C1–2, D2, GND D5–11, E4, E11, E2, F11, F1–2, G11, G2, H11, H2, J11, J1–4, K11, K2, L5–11, L2, M1–4 H12 LLBK G3 LOS C3 LOSLVL 26 I/O Signal Level I LVTTL Transmit DSPLL Bandwidth Select ...
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... The reference clock sets the operating frequency of the Si5100 transmit CMU, which is used to generate the high-speed transmit clock TXCLKOUT. The reference clock is also used by the Si5100 receiver CDR to cen- ter the PLL during lock acquisition, and as a ref- erence for determination of the receiver lock status. ...
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... Si5100 transmit CMU, which is used to generate the high-speed transmit clock TXCLKOUT. The reference clock is also used by the Si5100 receiver CDR to center the PLL dur- ing lock acquisition, and as a reference for deter- mination of the receiver lock status. When REFSEL = 0, the low-speed data input clock, TXCLK16IN, is used as the reference clock ...
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... This saves power in applications that do not require an auxiliary clock. Note: This input has an internal pullup. I High-Speed Differential Receive Data Input. Differential The receive clock and data signals RXCLK1, RXCLK2, and RXDOUT[15:0] are recovered from the high-speed data signal present on these pins. Rev. 1.4 Si5100 Description 29 ...
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... Si5100 Pin Number(s) Name G13 RXDOUT15+ H13 RXDOUT15– E14 RXDOUT14+ F14 RXDOUT14– E13 RXDOUT13+ F13 RXDOUT13– C14 RXDOUT12+ D14 RXDOUT12– C13 RXDOUT11+ D13 RXDOUT11– A14 RXDOUT10+ B14 RXDOUT10– B12 RXDOUT9+ B13 RXDOUT9– A12 RXDOUT8+ A13 RXDOUT8– ...
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... Note: This input has an internal pulldown. I LVDS Differential Transmit Data Clock Input. The rising edge of this input clocks data present on TXDIN into the device. TXCLK 16IN is also used as the Si5100 reference clock when the REFSEL input is set low. Rev. 1.4 Si5100 Description 31 ...
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... TXDOUT[15:0] word rate. This is accomplished by dividing by either 4 or 16, depending on the state of the MODE16 input. The TXCLK16OUT is provided for use in counter clocking schemes that transfer data between the system framer and the Si5100. (See REFSEL and REFRATE descriptions.) I LVTTL High-Speed Transmit Clock Disable. ...
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... TXMSBSEL input. The TXDOUT outputs are updated by the rising edge of TXCLKOUT. O LVTTL Transmit CMU Loss-of-Lock. The TXLOL output is asserted (low) when the CMU is not phase-locked to the selected refer- ence source or if REFCLK is not present. See LOL in Table 5 on page 10. Rev. 1.4 Si5100 Description 33 ...
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... O Voltage Ref Voltage Reference. The Si5100 provides an output voltage reference that can be used by an external circuit to set the LOS threshold, slicing level, or sampling phase adjustment. The equivalent resistance between this pin and GND should not be less than 10 k Ω . ...
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... Ordering Guide Part Number Si5100-G-BC Si5100-H-BL Si5100-H-GL Package Temperature Range 195-Ball CBGA – °C (Prior Revision) RoHS-5 195-Ball PBGA – °C (Current Revision) RoHS-5 195-Ball PBGA – °C (Current Revision) RoHS-6 Rev. 1.4 Si5100 35 ...
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... Si5100 19. Package Outline Figure 15 illustrates the package details for the Si5100. Table 9 lists the values for the dimensions shown in the illustration. Figure 15. 195-Ball Plastic Ball Grid Array (PBGA) Table 9. Package Diagram Dimensions (mm) Symbol Min Nom A 1.22 1.39 A1 0.40 0.50 A2 0.32 0. ...
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... The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Min Nom X 0.40 0.45 C1 13.00 C2 13.00 E1 1.00 E2 1.00 Rev. 1.4 Si5100 Max 0.50 37 ...
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... Si5100 OCUMENT HANGE IST Revision 0.7 to Revision 1.0 Updated 1. "Si5100 Detailed Block Diagram" on page 4 to clarify control of RXAMPMON and CMU timing source. Figure 1 on page 5 Clarified the measurement of V ICM Updated Table 3 on page 8. Updated Table 4 on page 9. Updated Table 5 on page 10. ...
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... N : OTES Rev. 1.4 Si5100 39 ...
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... Si5100 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: HighSpeed@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...