TP3410J National Semiconductor, TP3410J Datasheet - Page 20

• Manufacturer Part Number: TP3410J
• Manufacturer: National Semiconductor

Specifications of TP3410J

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
Receive D Channel Time-Slot Assignment Select
DR5–DR0 SR1–SR0
DR5 –DR0 bits define the binary number of the 8-bit wide
time-slot where the time-slots are numbered from 0 to 63
Within this selected time-slot the SR1 and SR0 bits define
the binary number of the 2 D channel bits Sub-slots are
numbered 0 to 3 as shown in Figure 12 and the following
table New time-slot and sub-slot assignments become ef-
fective only at the beginning of a frame
9 10 Configuration Register OPR
Overhead Bit Processing
This register controls the enabling disabling of conditions
which are sent to the Interrupt Stack (see 10 1) as a result
of new data in the RXM4 and RXM56 Overhead Bits Regis-
ters and the number of consecutive times a new bit or mes-
sage is received before being validated Flexibility is there-
fore provided to use hardware external firmware routines or
a combination of both for validation
Near-End CRC Interrupt Enable CIE
CIE
Block Error Counter Interrupt Enable EIE
EIE
febe Bit Interrupt Enable FIE
FIE
At Power-On Reset this register is initialized to X 08
At Power-On Reset this register is initialized to X 00
1
1
1
DR5
CIE
0
0
0
7
7
SR1
0
1
1
0
No Interrupt if near-end crc error (Block Error
Counters still count)
RXM56 Status Register Interrupt is generated with
NEB
generated crc result does not match the crc in the
received superframe
No Interrupt or Monitor channel message from
Block Error Counters
Block Error Counter Interrupts enabled
No Interrupt if febe
RXM56 Status Register Interrupt is generated with
RFB
received
DR4
EIE
6
6
Sub-Slot
e
e
FIE
0 each superframe in which the locally-
0 each superframe in which febe
DR3
5
5
SR0
0
1
0
1
OB1
DR2
4
4
Byte 2
Byte 2
e
0 received (BEC1 still counts)
DR1
OB0
3
3
within Time-Slot
Bit Positions
(Continued)
DR0
OC1
2
2
1 2
3 4
5 6
7 8
SR1
1
OC0
e
1
0 is
SR0
0
0
0
20
Receive Overhead Bits Interrupt Enable 0B1 0B0
These bits determine how many consecutive superframes
must be received with the same new data in any of the
overhead bit positions M41– M48 M51 M52 and or M61
before an Interrupt(s) is generated for the RXM4 and or
RXM56 Register as appropriate Note that validation check-
ing of the ‘‘act’’ and ‘‘dea’’ bits during activation deactiva-
tion is not affected by OB1 OB0
OB1
Receive Embedded Operations Channel Interrupt
Enable OC1 OC0
These bits determine how many consecutive half-super-
frames must be received with the same new address or data
in the Embedded Operations Channel before an Interrupt is
generated for the RX EOC Register
OC1
9 11 Transmit M4 Channel Register TXM4 (Write Only)
When the line is superframe synchronized the device trans-
mits the contents of this register to the line in the M4 over-
head bit field once per superframe
At Power-On Reset and each time the device is Deactivat-
ed (or an Activation attempt fails) this register is initialized
to X 7F
ACT Bit
The ACT bit in the TXM4 register does not normally control
the ‘‘act’’ bit in the M4 word transmitted to the line (see
Table I) That ‘‘act ’’ bit is generated automatically within the
device and can be controlled through the Activation Control
Register (see Table I and Section 11 0 Activation Deactiva-
tion) In normal operation the ACT bit in the TXM4 register is
ignored
M42– M48 Bits
As shown in the Frame Formats in Table I the functions of
these bits depend on the mode of the device They should
be programmed as appropriate prior to an Activation Re-
quest with the exception of the M42 bit in LT Mode This is
the dea bit which is automatically controlled by the device
in response to AR and DR commands the M42 bit in this
register is normally ignored in LT mode
ACT
0
1
1
0
1
1
0
0
7
OB0
OC0
M42
0
1
0
1
0
1
0
1
6
Interrupt every superframe (no checking)
Interrupt if any bit changed from previous
superframe
2 consecutive times for same new bit(s)
before Interrupt
3 consecutive times for same new bit(s)
before Interrupt
Interrupt every received eoc message (no
checking)
Interrupt every received eoc message
which differs from previous message
2 consecutive times for same new message
before Interrupt
3 consecutive times for same new message
before Interrupt
M43
5
M44
4
Byte 2
M45
3
M46
2
M47
1
M48
0