TP3420AV National Semiconductor, TP3420AV Datasheet - Page 27

• Manufacturer Part Number: TP3420AV
• Manufacturer: National Semiconductor

Specifications of TP3420AV

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Timing Diagrams
Definitions and Timing Conventions
DEFINITIONS
V
IH
V
input level is guaranteed to appear as a
logical one. This parameter is to be
measured by performing a functional
test at reduced clock speeds and nomi-
nal timing, (i.e. not minimum setup and
hold times or output strobes), with the
high level of all driving signals set to V
and maximum supply voltages applied
to the device.
IH
is the d.c. input level above which an
(Continued)
FIGURE 10. Timing Details for Digital System Interface
FIGURE 11. Timing Details for TEM, DCKE Mode
IH
27
V
V
IL
OH
V
input level is guaranteed to appear as a
logical zero to the device. This param-
eter is measured in the same manner as
V
set to V
applied to the device.
V
which an output placed in a logical one
state will converge when loaded at the
maximum specified load current.
IL
IH
OH
is the d.c. input level below which an
but with all driving signal low levels
is the minimum d.c. output level to
IL
DS009143-27
and minimum supply voltages
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DS009143-26