Core1553B Eval Board MICROSEMI, Core1553B Eval Board Datasheet
Core1553B Eval Board
Specifications of Core1553B Eval Board
Related parts for Core1553B Eval Board
Core1553B Eval Board Summary of contents
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Core1553BBC MIL-STD-1553B Bus Controller Product Summary Intended Use • 1553B Bus Controller (BC) • DMA Backend Interface to External Memory Key Features • Supports MIL-STD-1553B • Interfaces to External RAM – Supports up to 128kbytes of Memory – Synchronous or ...
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Core1553BBC MIL-STD-1553B Bus Controller General Description The Core1553BBC provides a complete, MIL-STD-1553B Bus Controller (BC). A typical system implementation using the Core1553BBC is shown in Core1553BBC reads message descriptor blocks from the memory and generates messages that are transmitted on ...
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A single 1553B encoder takes each word to be transmitted and serializes it using Manchester encoding. The encoder includes independent logic to prevent the BC from transmitting for greater than the allowed period and to provide loopback fail logic. The ...
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Core1553BBC MIL-STD-1553B Bus Controller Core1553BBC Device Requirements The Core1553BBC can be implemented in several Actel FPGA devices. Core1553BBC implemented in these devices. Table 1 • Device Utilization Family Combinatorial Fusion ProASIC3/E PLUS ProASIC Axcelerator RTAX-S SX-A RTSX-S The Core1553BBC clock ...
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Message Types The 1553B bus supports ten message transfer types, allowing basic point-to-point and broadcast data transfers, mode code messages, and direct RT-to-RT messages. BC-to-RT Transfer BC Transmit Data Data Command RT-to-BC Transfer ...
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Core1553BBC MIL-STD-1553B Bus Controller Word Formats There are only three types of words in a 1553B message: a command word (CW), a data word (DW), and a status word (SW). Each 20-bit word consists of a 3-bit sync pattern, 16 ...
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Table 3 • Control and Status Signals Name Type Description CLK In Master clock input (either 12 MHz, 16 MHz, 20 MHz MHz) RSTINn In Reset input (active low) INTOUT Out Interrupt Request (active high). The CPU is ...
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Core1553BBC MIL-STD-1553B Bus Controller Backend Interface The backend interface supports both synchronous operation and asynchronous operation to backend devices. Synchronous operation directly supports the use of internal FPGA memory blocks. Asynchronous operation allows connection to standard external memory devices. Table ...
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Miscellaneous I/O Several inputs are used to modify the core functionality to simplify integration in the application. These inputs should be tied to logic '0' or logic '1' as appropriate Table 6 • Memory Access Requirements CPUMEMEN CLK Speed MHz ...
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Core1553BBC MIL-STD-1553B Bus Controller Table 8 • Bus Controller Registers Address Name Type 110 STACKPTR RW 111 INTERRUPT RW Table 9 • Setup Register Bits Name Type Reset 15 FORCEORUN RW 14 CLOCKEN RW 13:12 CLKFREQ RW 11 RETRYMODE WR ...
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Table 9 • Setup Register (Continued) Bits Name Type Reset 3:2 RESPTIME RW 1:0 Reserved R Table 10 • Control Register Bits Name Type Function 3 ASYNC W Writing a '1' causes the bus controller to jump to process the ...
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Core1553BBC MIL-STD-1553B Bus Controller Table 12 • Interrupt Register Bits Name Type Function 15 INTPENDING RW When set, the BC has an interrupt pending. This bit is set if any of the INTVECT bits are set. 14:8 INTVECT RW Interrupt ...
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Bus Controller Operation After power-up, the bus controller waits while the CPU sets up the bus controller memory and registers. The memory contains an instruction list, message blocks, and data blocks. Once the instruction list, message blocks, and data blocks ...
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Core1553BBC MIL-STD-1553B Bus Controller Table 14 • Supported Instructions (Continued) OPCODE Function Condition Code Parameter 0110 LOADC Yes 0111 WAITC Yes 1000 CALL Yes 1001 RET Yes 1010 RETAS Yes 1011 STOREF Yes Others Illegal N/A Table 15 • Condition ...
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Table 15 • Condition Codes (Continued) Condition Code Function Description 10111 NBR Performs the instruction if the Broadcast Received bit was not set in the last received status word 11000 NSR Performs the instruction if the Service Request bit was ...
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Core1553BBC MIL-STD-1553B Bus Controller Message Block An 8-word message block controls each message. The BC reads the 1553B command words from the message block and will write the received status words back to message block. Message blocks must be positioned ...
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Table 16 • Message Block (Continued) Offset Contents Written by Description 6 TSW BC 7 Reserved – Message Transfer Status Word. Provides status information on the message block. The CPU should clear this field when setting up the message block ...
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Core1553BBC MIL-STD-1553B Bus Controller Detailed Operation Flow Table 17 shows the operations the core goes through in processing a message list containing two messages. The first message is a BC-to-RT transfer of three words, and the second is an RT-to-BC ...
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Error Conditions Core1553BBC monitors bus errors and in most cases will perform automatic retry operations if recovery is possible (Table 18). Table 18 • Error Conditions Error Condition Group Error Signaling 1553B signaling error, parity, Manchester error, too many or ...
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Core1553BBC MIL-STD-1553B Bus Controller Asynchronous Messages Core1553BBC supports asynchronous messages. While idle, or when a normal message list is being processed, the CPU can initiate the core to jump to a secondary (asynchronous) message list and process these messages. When ...
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Memory 64K*16 PCI Interface Development PCB Figure 7 • Core1553BBC Development System Core1553BBC MIL-STD-1553B Bus Controller Memory Access PCI Target Interface Core1553BBC Actel FPGA v4.0 Pulse Transformer Pulse Transceiver Transformer 21 ...
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Core1553BBC MIL-STD-1553B Bus Controller Typical BC System Core1553BBC requires a master CPU to set up the data tables. The CPU needs to be able to access the internal core registers as well as the backend memory. Core1553BBC can be configured ...
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Memory Bus Arbritator CPU Figure 9 • Core1553BBC Using Shared Memory Core1553BBC MIL-STD-1553B Bus Controller BUSAINEN RCVSTBA BUSAINP RXDAIN BUSAINN RXDAIN BUSAOUTINH TXINHA BUSAOUTP TXDAIN BUSAOUTN TXDAIN Transceiver BUSBINEN RCVSTBA BUSBINP RXDBIN BUSBIN RXDBIN BUSAOUTINH TXINHA BUSBOUTP TXDBIN BUSBOUTN TXDBIN ...
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Core1553BBC MIL-STD-1553B Bus Controller Specifications CPU Interface Timing CPUCSN CPURDN CPUADDR CPUMEM CPUDOUT CPUDEN CPUWAITN Figure 10 • CPU Interface Register Read Cycle CLK CPUCSN CPUWRN[1:0] CPUADDR CPUMEM CPUDIN CPUWAITN Figure 11 • CPU Interface Register Write Cycle CLK CPUCSN ...
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CLK CPUCSN CPUWRN CPUADDR CPUMEM CPUDIN CPUWAITN Figure 13 • CPU Interface Memory Write Cycle CPUWAITn will be driven low for a minimum of three (3) clock cycles for write cycles, four (4) for read cycles, and the number of ...
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Core1553BBC MIL-STD-1553B Bus Controller CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMDOUT MEMWRn MEMWAITn Figure 16 • Asynchronous Memory Write Cycle CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn MEMADDR MEMDIN MEMWAITn Figure 17 • Synchronous Memory Read Cycle CLK MEMREQn ...
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CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn MEMADDR MEMDIN MEMWAITn Figure 19 • Synchronous Memory Read Cycle with MEMGNTn Active CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMADDR MEMDOUT MEMWRn MEMWAITn Figure 20 • Synchronous Memory Write Cycle with MEMGNTn Active ...
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Core1553BBC MIL-STD-1553B Bus Controller CLK MEMREQn MEMGNTn MEMCEN MEMDEN MEMCSn MEMRDn/WRn MEMWAITn MEMFAIL Figure 22 • Memory Wait Time-out Clock Requirements To meet the 1553B transmission bit rate requirements, the Core1553BBC clock input must be 12, 16, 20 ...
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List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version ( v3.0 The "Supported Families" section Table 1 was updated to include ...
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