MAX8556ETE+ Maxim, MAX8556ETE+ Datasheet - Page 8

• Manufacturer Part Number: MAX8556ETE+
• Description: Voltage Regulator, Linear, LDO, Ultra-Low 1.425-3.6 Vin, 4 Aout, QFN-15
• Manufacturer: Maxim
• Type: Voltage Regulatorr

Specifications of MAX8556ETE+

• Current, Input Bias: 0.001 μA
• Current, Output: 0.001 μA
• Current, Supply: 800 μA
• Package Type: Thin QFN
• Power Dissipation: 2666.7 mW
• Regulation, Line: ±0.15 %/V
• Regulation, Load: 0.1 %/A
• Regulator Type: Low Dropout
• Temperature, Operating, Range: -40 to +85 °C
• Voltage, Dropout: 100 mV
• Voltage, Output: 0.5 to 3.4 V
• Voltage, Output, Low: 25 mV
• Voltage, Supply: 1.425 to 3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

How much power the package can dissipate strongly
depends on the mounting method of the IC to the PC
board and the copper area for cooling. Using the
JEDEC test standard, the maximum power dissipation
allowed in the package is 2667mW. This data is
obtained with +70°C ambient temperature and +150°C
maximum junction temperature. The test board has
dimensions of 3in x 3in with four layers of 2oz copper
and FR-4 material with 62mil finished thickness. Nine
thermal vias are used under the thermal paddle with a
diameter of 12mil and 1mil plated copper thickness.
Top and bottom layers are used to route the traces.
Two middle layers are solid copper and isolated from
the nine thermal vias.
More power dissipation can be handled by the pack-
age if great attention is given during PC board layout.
For example, using the top and bottom copper as a
heatsink and connecting the thermal vias to one of the
middle layers (GND) transfers the heat from the pack-
age into the board more efficiently, resulting in lower
junction temperature at high power dissipation in some
MAX8556/MAX8557 applications. Furthermore, the sol-
der mask around the IC area on both top and bottom
layers can be removed to radiate the heat directly into
the air. The maximum allowable power dissipation in
the IC is as follows:
TRANSISTOR COUNT: 3137
PROCESS: BiCMOS
P
MAX
_______________________________________________________________________________________
=
Thermal Considerations
(
T
J MAX
θ
Chip Information
(
JC
in PC Board Layout
+
)
θ
CA
−
T
A
)
4A Ultra-Low-Input-Voltage
where T
(+150°C), T
(1.7°C/W for the 16-pin TQFN) is the thermal resistance
from the junction to the case, and θ
resistance from the case to the surrounding air through
the PC board, copper traces, and the package materi-
als. θ
can be modified to increase the maximum power dissi-
pation. The TQFN package has an exposed thermal
pad on its underside. This pad provides a low thermal
resistance path for heat transfer into the PC board. This
low thermally resistive path carries a majority of the
heat away from the IC. The PC board is effectively a
heatsink for the IC.
The exposed paddle should be connected to a large
ground plane for proper thermal and electrical perfor-
mance. The minimum size of the ground plane is
dependent upon many system variables. To create an
efficient path, the exposed paddle should be soldered
to a thermal landing, which is connected to the ground
plane by thermal vias. The thermal landing should be at
least as large as the exposed paddle and can be made
larger depending on the amount of free space from the
exposed paddle to the other pin landings.
A sample layout is available on the MAX8556 evalua-
tion kit to speed designs.
PACKAGE TYPE
CA
16 TQFN
J(MAX)
is directly related to system level variables and
A
is the ambient air temperature, θ
is the maximum junction temperature
LDO Regulators
PACKAGE CODE
Package Information
T1655-2
CA
DOCUMENT NO.
is the thermal
21-0140
JC
9