PIC16LF1826-I/SS Microchip Technology Inc., PIC16LF1826-I/SS Datasheet - Page 263
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PIC16LF1826-I/SS
Manufacturer Part Number
PIC16LF1826-I/SS
Description
3.5 KB Flash, 256 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, n
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F1826-ISO.pdf
(406 pages)
Specifications of PIC16LF1826-I/SS
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
8 MIPS
Eeprom Memory
256 Bytes
Input Output
16
Interface
I2C/SPI/UART/USART
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin SSOP
Programmable Memory
3.5K Bytes
Ram Size
256 Bytes
Speed
32 MHz
Temperature Range
–40 to 125 °C
Timers
2-8-bit, 1-16-bit
Voltage, Range
1.8-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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25.6.2
Clock arbitration occurs when the master, during any
receive, transmit or Repeated Start/Stop condition,
releases the SCLx pin (SCLx allowed to float high).
When the SCLx pin is allowed to float high, the Baud
Rate Generator (BRG) is suspended from counting
until the SCLx pin is actually sampled high. When the
SCLx pin is sampled high, the Baud Rate Generator is
reloaded with the contents of SSPxADD<7:0> and
begins counting. This ensures that the SCLx high time
will always be at least one BRG rollover count in the
event that the clock is held low by an external device
(Figure
FIGURE 25-25:
25.6.3
If the user writes the SSPxBUF when a Start, Restart,
Stop, Receive or Transmit sequence is in progress, the
WCOL is set and the contents of the buffer are
unchanged (the write does not occur). Any time the
WCOL bit is set it indicates that an action on SSPxBUF
was attempted while the module was not Idle.
2011 Microchip Technology Inc.
Note:
25-25).
CLOCK ARBITRATION
WCOL STATUS FLAG
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPxCON2 is disabled until the Start
condition is complete.
SDAx
SCLx
BRG
Value
BRG
Reload
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
03h
DX
SCLx deasserted but slave holds
SCLx low (clock arbitration)
02h
SCLx is sampled high, reload takes
place and BRG starts its count
01h
BRG decrements on
Q2 and Q4 cycles
00h (hold off)
DX ‚
–
PIC16(L)F1826/27
1
SCLx allowed to transition high
03h
02h
DS41391D-page 263
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