DS90C241QVS National Semiconductor, DS90C241QVS Datasheet - Page 14

• Manufacturer Part Number: DS90C241QVS
• Manufacturer: National Semiconductor

Specifications of DS90C241QVS

• Number Of Elements: 1
• Number Of Receivers: 24
• Number Of Drivers: 1
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Output Type: Serializer
• Differential Output Voltage: 1.2V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

www.national.com
LVCMOS PARALLEL INTERFACE PINS
25-28,
31-34
13-16,
21-24
3-6,
9-12
18
CONTROL AND CONFIGURATION PINS
43
48
1
17
2
LVDS SERIAL INTERFACE PINS
41
42
POWER / GROUND PINS
39
40
47
46
45
44
37
38
36
35
30
29
20
19
7
8
Pin #
DS90C124 Deserializer Pin Descriptions
ROUT[7:0]
ROUT[15:8]
ROUT[23:16] LVCMOS_O
RCLK
RRFB
REN
RPWDNB
LOCK
RESRVD
RIN+
RIN−
VDDIR
VSSIR
VDDPR0
VSSPR0
VDDPR1
VSSPR1
VDDR1
VSSR1
VDDR0
VSSR0
VDDOR1
VSSOR1
VDDOR2
VSSOR2
VDDOR3
VSSOR3
Pin Name
LVCMOS_O
LVCMOS_O
LVCMOS_O
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVCMOS_O
LVCMOS_I
LVDS_I
LVDS_I
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
I/O
Receiver LVCMOS level Outputs – Group 1
Receiver LVCMOS level Outputs – Group 2
Receiver LVCMOS level Outputs – Group 3
Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
Receiver Clock Edge Select Pin
RRFB = H; R
RRFB = L; R
Receiver Data Enable
REN = H; R
REN = L; R
are in TRI-STATE, PLL still operational and locked to TCLK.
Receiver Power Down Bar
RPWDNB = H; Receiver is Enabled and ON
RPWDNB = L; Receiver is in power down mode (Sleep), R
TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
LOCK indicates the status of the receiver PLL
LOCK = H; receiver PLL is locked
LOCK = L; receiver PLL is unlocked, R
Reserved. This pin MUST be tied LOW.
Receiver LVDS True (+) Input
This input is intended to be terminated with a 100Ω load to the R
be AC Coupled to this pin with a 100 nF capacitor.
Receiver LVDS Inverted (−) Input
This input is intended to be terminated with a 100Ω load to the R
be AC Coupled to this pin with a 100 nF capacitor.
Analog LVDS Voltage supply, Power
Analog LVDS Ground
Analog Voltage supply, PLL Power
Analog Ground, PLL Ground
Analog Voltage supply, PLL VCO Power
Analog Ground, PLL VCO Ground
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
Digital Voltage supply, Logic Power
Digital Ground, Logic Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
Digital Voltage supply, LVCMOS Output Power
Digital Ground, LVCMOS Output Ground
OUT
OUT
OUT
OUT
[23-0] and RCLK are Disabled (OFF), Receiver R
[23-0] and RCLK are Enabled (ON).
LVCMOS Outputs strobed on the Falling Clock Edge.
LVCMOS Outputs strobed on the Rising Clock Edge.
14
OUT
Description
[23-0] and RCLK are TRI-STATED
OUT
[23-0], RCLK, and LOCK are in
IN+
IN-
OUT
pin. The interconnect should
pin. The interconnect should
[23-0] and RCLK Outputs