ADC10065CIMT/HALF National Semiconductor, ADC10065CIMT/HALF Datasheet - Page 6

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ADC10065CIMT/HALF

Manufacturer Part Number
ADC10065CIMT/HALF
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of ADC10065CIMT/HALF

Lead Free Status / Rohs Status
Supplier Unconfirmed
www.national.com
CLK, DF, STBY, SENSE
D0–D9 OUTPUT CHARACTERISTICS
DYNAMIC CONVERTER CHARACTERISTICS (Note 13)
ENOB
SNR
SINAD
2nd HD
3rd HD
THD
SFDR
DC and Logic Electrical Characteristics
for V
Cycle, C
SSA
Symbol
= V
L
= 10 pF/pin. Boldface limits apply for T
SSIO
= 0V, V
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Input Current
Logical “0” Input Current
Logical “1” Output Voltage
Logical “0” Output Voltage
Effective Number of Bits
Signal-to-Noise Ratio
Signal-to-Noise Ratio + Distortion
2nd Harmonic
3rd Harmonic
Total Harmonic Distortion (First 6
Harmonics)
Spurious Free Dynamic Range
(Excluding 2nd and 3rd Harmonic)
DDA
= +3.0V, V
Parameter
DDIO
= +2.5V, V
A
= T
IN
MIN
= 2 V
to T
Conditions
I
I
f
f
f
f
f
f
f
f
f
f
f
f
f
f
P-P
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
6
MAX
, STBY = 0V, V
= 11 MHz
= 32 MHz
= 11 MHz
= 32 MHz
= 11 MHz
= 32 MHz
= 11 MHz
= 32 MHz
= 11 MHz
= 32 MHz
= 11 MHz
= 32 MHz
= 11 MHz
= 32 MHz
= −0.5 mA
= 1.6 mA
: all other limits T
Unless otherwise specified, the following specifications apply
REF
= 1.20V (External), f
A
= 25°C
−66.2, −63
−66.2, −63
V
58.5, 57.9
58.3, 57.6
58.6, 58
58, 57.4
9.4, 9.3
9.3, 9.2
DDIO
−75.6,
−72.7,
−65.4,
−65.4,
−75.8,
−74.4,
−69.7
−68.9
−63.3
−63.3
−74.5
−73.3
Min
−10
2
−0.2
59.6
59.3
59.4
Typ
−90
−82
−74
−72
−74
−72
−80
−80
9.6
9.5
59
CLK
= 65 MHz, 50% Duty
Max
+10
0.8
0.4
Units
dBc
dBc
dBc
dBc
dBc
dBc
Bits
Bits
µA
µA
dB
dB
dB
dB
dB
dB
V
V
V
V