CLC5526PCASM/NOPB National Semiconductor, CLC5526PCASM/NOPB Datasheet - Page 9

• Manufacturer Part Number: CLC5526PCASM/NOPB
• Manufacturer: National Semiconductor

Specifications of CLC5526PCASM/NOPB

• Lead Free Status / Rohs Status: Compliant

Applications
Stray capacitance at the output, along with the output load
value will form a pole, which can degrade the CLC5526
bandwidth. For a narrow-band application this problem can
be alleviated by using a tuned load, which will incorporate
any stray parasitic impedance into a resonant circuit. By
tuning the resonant load, full gain can be achieved with a
given resistive load.
A typical tuned load is shown below in Figure 3, where the
resonant frequency is tuned about 150 MHz.
The 1000Ω load in this circuit can represent the input imped-
ance of the CLC5957 Analog to Digital converter. Actual
values for the reactive components may vary slightly to
account for board and device parasitic elements.
The Diversity Receiver Chipset may also use the
ADC12L066 A/D converter in place of the CLC5957. Please
refer to the Low Power Diversity Receiver Chipset (LDRCS)
User’s Guide for input matching between the CLC5526 and
ADC12L066.
Typical Application
Although the CLC5526 can be used as a general purpose
digital variable gain amplifier, it was specifically designed to
provide the variable gain function in National’s Diversity
Receiver Chipset. In this application, the CLC5526 drives a
tuned BPF and the CLC5957 Analog to Digital converter.
Digitized IF data is downsampled and tuned with the
CLC5903 dual digital tuner which also provides the AGC
control function. AGC data is fed back to the CLC5526. The
FIGURE 3. CLC5526 Driving a Tuned Load
Chart 1: Maximum Gain vs R
(Continued)
LOAD
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CLC5957 differential input impedance is 1000Ω, so with the
tuned load, full gain of the CLC5526 is achieved. Figure 4
shows the block diagram of the Diversity Receiver Chipset
application. Figure 5 shows the SINAD vs Input Power of the
diversity receiver chipset. For input power levels ranging
from 0 dB to −110 dB, the chip set provides a signal to noise
ratio in excess of the 9 dB required for a typical GSM system.
Layout Considerations
A proper printed circuit layout is essential for achieving high
frequency performance. National Semiconductor provides
evaluation boards for the CLC5526, which include input and
output transformers for impedance matching and single to
differential signal conversion.
Supply bypassing is required for best performance. Provide
a 6.8 µF Tantalum and 0.1 µF ceramic capacitor as close as
possible to the supply pin.
In addition, a 100 pF ceramic capacitor should be placed
between the COMP pin (pin 9) and the system ground. This
will filter high frequency noise from the common-mode level.
Ceramic coupling capacitors should be used to AC couple
both the input and output. Actual values will depend upon the
signal frequency.
FIGURE 4. Diversity Receiver Chipset Block Diagram
FIGURE 5. Diversity Receiver Chipset
SINAD vs Input Power
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