LFE2M70E-6FN900C Lattice, LFE2M70E-6FN900C Datasheet - Page 38
LFE2M70E-6FN900C
Manufacturer Part Number
LFE2M70E-6FN900C
Description
IC, LATTICEECP2M FPGA, 420MHZ, FPBGA-900
Manufacturer
Lattice
Series
LatticeECP2Mr
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2M70E-6FN900C
No. Of Logic Blocks
67000
No. Of Macrocells
34000
No. Of Speed Grades
6
Total Ram Bits
4534Kbit
No. Of I/o's
416
Clock Management
DLL, PLL
I/o Supply Voltage
3.465V
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M70E-6FN900C
Manufacturer:
LATTICE
Quantity:
47
Company:
Part Number:
LFE2M70E-6FN900C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Top Edge
The PICs on the top edge are different from PIOs on the left, right and bottom edges. PIOs on this edge do not
have registers or DQS signals.
The exact DQS pins are shown in a dual function in the Logic Signal Connections table in this data sheet. Addi-
tional detail is provided in the Signal Descriptions table. The DQS signal from the bus is used to strobe the DDR
data from the memory into input register blocks. Interfaces on the left and right edges are designed for DDR mem-
ories that support 16 bits of data, whereas interfaces on the bottom are designed for memories that support 18 bits
of data.
Figure 2-33. DQS Input Routing for the Left and Right Edges of the Device
DQS
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
PIO A
PIO B
2-35
sysIO
Buffer
Delay
LatticeECP2/M Family Data Sheet
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADA "T"
PADB "C"
PADB "C"
PADA "T"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
PADB "C"
DQS Pin
PADA "T"
PADB "C"
Assigned
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
LVDS Pair
Architecture
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