AD5755-1ACPZ Analog Devices Inc, AD5755-1ACPZ Datasheet - Page 29

• Manufacturer Part Number: AD5755-1ACPZ
• Description: 16Bit Quad,V/I DAC No Dynamic Power Ctrl
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of AD5755-1ACPZ

• Input Channel Type: Serial
• Data Interface: 3-Wire, Serial
• Supply Voltage Range - Digital: 2.7V To 5.5V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 64
• Operating Temperature Range: -40°C To +105°C
• Rohs Compliant: Yes
• Resolution (bits): 16bit
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Featured Product: AD5755 / AD5755-1 / AD5757 DACs
• Settling Time: 11µs
• Number Of Bits: 16
• Number Of Converters: 4
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): -
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 64-VFQFN Exposed Pad, CSP
• Number Of Outputs And Type: 4 Current, 4 Voltage
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

with all zeros. This means that if the user clears the part after
power-up, the output is actively driven to 0 V (if the channel
has been enabled for clear).
SERIAL INTERFACE
The AD5755-1 is controlled over a versatile 3-wire serial
interface that operates at clock rates of up to 30 MHz and is
compatible with SPI, QSPI, MICROWIRE, and DSP standards.
Data coding is always straight binary.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the falling edge of SCLK.
If packet error checking, or PEC (see the Device Features
section), is enabled, an additional eight bits must be written to
the AD5755-1, creating a 32-bit serial interface.
There are two ways in which the DAC outputs can be updated:
individual updating or simultaneous updating of all DACs.
Individual DAC Updating
In this mode, LDAC is held low while data is being clocked into
the DAC data register. The addressed DAC output is updated on
the rising edge of SYNC . See
information.
Simultaneous Updating of All DACs
In this mode, LDAC is held high while data is being clocked
into the DAC data register. Only the first write to each channel’s
DAC data register is valid after LDAC is brought high. Any subse-
quent writes while LDAC is still held high are ignored, though
they are loaded into the DAC data register. All the DAC outputs
are updated by taking LDAC low after SYNC is taken high.
Table 3
and
Figure 3
for timing
Rev. A | Page 29 of 48
TRANSFER FUNCTION
Table 6 shows the input code to ideal output voltage relationship
for the AD5755-1 for straight binary data coding of the ±10 V
output range.
Table 6. Ideal Output Voltage to Input Code Relationship
1111
1111
1000
0000
0000
Straight Binary Data Coding
MSB
Figure 74. Simplified Serial Interface of Input Loading Circuitry
V
REFIN
1111
1111
0000
0000
0000
LDAC
SYNC
SCLK
SDIN
Digital Input
1111
1111
0000
0000
0000
DAC INPUT
INTERFACE
REGISTER
DAC DATA
REGISTER
REGISTER
for One DAC Channel
LSB
16-BIT
DAC
LOGIC
DAC
1111
1110
0000
0001
0000
I/V AMPLIFIER
CALIBRATION
Analog Output
V
+2 V
+2 V
0 V
−2 V
−2 V
OUTPUT
AND GAIN
OFFSET
OUT
SDO
REF
REF
REF
REF
× (32,767/32,768)
× (32,766/32,768)
× (32,767/32,768)
AD5755-1
V
OUT_x