MC9S08GW64CLH Freescale Semiconductor, MC9S08GW64CLH Datasheet
MC9S08GW64CLH
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MC9S08GW64 MC9S08GW32 Reference Manual HCS08 Microcontrollers MC9S08GW64RM Rev.3 10/2010 freescale.com Related Documentation: • MC9S08GW64 (Data Sheet) Contains pin assignments and diagrams, all electrical specifications, and mechanical drawing outlines. Find the most current versions of all documents at: http://www.freescale.com ...
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MC9S08GW64 Features 8-Bit HCS08 Central Processor Unit (CPU) • New version of S08 core with same performance as traditional S08 and lower power • MHz CPU at 3 2.15 V and up to 10MHz CPU ...
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MC9S08GW64 MCU Series Reference Manual Covers: MC9S08GW64 MC9S08GW32 MC9S08GW64 Rev.3 10/2010 ...
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... Updated Updated Updated Updated the Updated the This product incorporates SuperFlash Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. Freescale Semiconductor, Inc., 2009-2010. All rights reserved. MC9S08GW64 MCU Series Reference Manual, Rev.3 6 Description of Changes Table 4-3; corrected PRACMPxC0 register in the Figure 4-2 ...
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... Chapter 15 16-Bit Modulo Timer (S08MTIM16V1 353 Chapter 16 Independent Real Time Clock (IRTCV2 363 Chapter 17 Analog-to-Digital Converter (ADC16V1 403 Chapter 18 FlexTimer Module (S08FTMV3 449 Chapter 19 Programmable Reference Analog Comparator (S08PRACMPV1 473 Chapter 20 Programmable Cyclic Redundancy Check (PCRCV1 485 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor 7 ...
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... Chapter 21 Position Counter (S08PCNTV1 495 Chapter 22 Programmable Delay Block (S08PDBV1 529 Chapter 23 Voltage Reference (VREFV1 541 Chapter 24 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 Chapter 25 Break Point Unit (BKPT) (64K 559 MC9S08GW64 MCU Series Reference Manual, Rev.3 8 Freescale Semiconductor ...
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... Active Background Mode ...............................................................................................................50 3.5 Wait Mode .......................................................................................................................................51 3.5.1 Low-Power Wait Mode (LPWait) .....................................................................................51 3.5.1.1 Interrupts in Low-Power Wait Mode ..............................................................52 3.5.1.2 Resets in Low-Power Wait Mode ...................................................................52 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Contents Title Chapter 1 Device Overview Chapter 2 Pins and Connections Chapter 3 Modes of Operation ...
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... Flash Clock Divider Register (FCDIV) ............................................................................93 4.9.2 Flash Options Register (FOPT and NVOPT) ....................................................................94 4.9.3 Flash Configuration Register (FCNFG) ...........................................................................95 4.9.4 Flash Protection Register (FPROT and NVPROT) ..........................................................95 4.9.5 Flash Status Register (FSTAT) ..........................................................................................96 4.9.6 Flash Command Register (FCMD) ...................................................................................97 MC9S08GW64 MCU Series Reference Manual, Rev.3 10 Chapter 4 Memory Freescale Semiconductor ...
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... System Clock Gating Control 5 Register (SCGC5) ........................................................127 6.1 Introduction ...................................................................................................................................129 6.2 Port Data and Data Direction ........................................................................................................129 6.3 Pullup, Slew Rate, and Drive Strength ..........................................................................................130 6.3.1 Port Internal Pullup Enable .............................................................................................130 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Chapter 6 Parallel Input/Output Control 11 ...
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... Port F Data Register (PTFD) ........................................................................148 6.6.6.2 Port F Data Direction Register (PTFDD) .....................................................148 6.6.6.3 Port F Pull Enable Register (PTFPE) ............................................................149 6.6.6.4 Port F Slew Rate Enable Register (PTFSE) ..................................................149 6.6.6.5 Port F Input Filter Enable Register (PTFIFE) ...............................................149 MC9S08GW64 MCU Series Reference Manual, Rev.3 12 Freescale Semiconductor ...
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... Port G Pin Function Register 1 (PTGPF1) ......................................................................170 6.7.26 Port G Pin Function Register 2 (PTGPF2) ......................................................................170 6.7.27 Port G Pin Function Register 3 (PTGPF3) ......................................................................171 6.7.28 Port G Pin Function Register 4 (PTGPF4) ......................................................................172 6.7.29 Port H Pin Function Register 1 (PTHPF1) ......................................................................173 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor 13 ...
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... KBI in Stop Modes .......................................................................................199 8.1.3.3 KBI in Active Background Mode .................................................................199 8.1.4 Block Diagram ................................................................................................................199 8.2 External Signal Description ..........................................................................................................200 8.3 Register Definition ........................................................................................................................200 8.3.1 KBI Status and Control Register (KBISC) .....................................................................200 MC9S08GW64 MCU Series Reference Manual, Rev.3 14 Chapter 7 Chapter 8 Keyboard Interrupt (S08KBIV2) Freescale Semiconductor ...
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... SPI Clock Formats ..........................................................................................................218 9.5.5 Special Features ..............................................................................................................220 9.5.5.1 SS Output ......................................................................................................220 9.5.5.2 Bidirectional Mode (MOMI or SISO) ..........................................................221 9.5.6 SPI Interrupts ..................................................................................................................222 9.5.7 Mode Fault Detection .....................................................................................................222 Serial Communication Interface (S08SCIV4) 10.1 Introduction ...................................................................................................................................223 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 9 Chapter 10 15 ...
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... External Signal Description ..........................................................................................................248 11.2.1 LCD[63:0] .......................................................................................................................249 11.2.2 V LCD ................................................................................................................................................................ 249 11.2 VLL2, V LL1 LL3 ...................................................................................................................................... 249 11.2.4 Vcap1, Vcap2 ..................................................................................................................249 11.3 Register Definition ........................................................................................................................249 11.3.1 LCD Control Register 0 (LCDC0) ..................................................................................249 MC9S08GW64 MCU Series Reference Manual, Rev.3 16 Chapter 11 LCD Module (S08LCDLPV1) Freescale Semiconductor ...
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... Stop Mode Recovery .......................................................................................................293 Inter-Integrated Circuit (S08IICV5) 12.1 Introduction ...................................................................................................................................295 12.1.1 IIC Clock Gating .............................................................................................................295 12.1.2 Features ...........................................................................................................................297 12.1.3 Modes of Operation ........................................................................................................297 12.1.4 Block Diagram ................................................................................................................297 12.2 External Signal Description ..........................................................................................................298 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 12 17 ...
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... Exit from Low-Power/Stop Modes .................................................................................319 12.6.4 Arbitration Lost Interrupt ................................................................................................319 12.6.5 Timeouts Interrupt in SMBus .........................................................................................320 12.6.6 Programmable Input Glitch Filter ...................................................................................320 12.6.7 Address Matching Wakeup .............................................................................................320 12.7 Initialization/Application Information ..........................................................................................321 12.8 SMBALERT# ................................................................................................................................325 MC9S08GW64 MCU Series Reference Manual, Rev.3 18 Freescale Semiconductor ...
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... Local Clock .....................................................................................................................341 8-Bit Modulo Timer (S08MTIMV1) 14.1 Introduction ...................................................................................................................................343 14.1.1 MTIM Clock Gating .......................................................................................................343 14.1.2 Features ...........................................................................................................................345 14.1.3 Modes of Operation ........................................................................................................345 14.1.3.1 MTIM in Wait Mode .....................................................................................345 14.1.3.2 MTIM in Stop Modes ...................................................................................345 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 13 Chapter 14 19 ...
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... Low Power Modes ..........................................................................................................368 16.3.1.1 Run Mode .....................................................................................................368 16.3.1.2 Wait Mode .....................................................................................................368 16.3.1.3 Stop Mode .....................................................................................................368 16.4 External Signal Description ..........................................................................................................368 16.5 Register Definitions .......................................................................................................................368 16.5.1 IRTC Year & Month Counters Register (IRTC_YEARMON) .......................................369 MC9S08GW64 MCU Series Reference Manual, Rev.3 20 Chapter 15 Chapter 16 Freescale Semiconductor ...
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... Hardware Trigger ............................................................................................................403 17.1.3 ADC Alternate Clock ......................................................................................................404 17.2 ADC Connections .........................................................................................................................404 17.2.1 Features ...........................................................................................................................407 17.2.2 Block Diagram ................................................................................................................407 17.3 External Signal Description ..........................................................................................................408 17.3.1 Analog Power (V 17.3.2 Analog Ground (V MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 17 ) ....................................................................................................409 DDA ) ...................................................................................................409 SSA 21 ...
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... Stop3 Mode With ADACK Disabled ............................................................441 17.5.11.2 Stop3 Mode With ADACK Enabled .............................................................441 17.5.12MCU Stop2 Mode Operation ..........................................................................................441 17.6 Initialization Information ..............................................................................................................441 17.6.1 ADC Module Initialization Example ..............................................................................442 MC9S08GW64 MCU Series Reference Manual, Rev .......................................................................409 REFSH ) ..........................................................................409 REFL Freescale Semiconductor ...
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... Counter Clock Source ...................................................................................461 18.4.2 Prescaler ..........................................................................................................................462 18.4.3 Counter ............................................................................................................................462 18.4.3.1 Up Counting ..................................................................................................462 18.4.3.2 Up-Down Counting .......................................................................................463 18.4.3.3 Free Running Counter ...................................................................................464 18.4.3.4 Counter Reset ................................................................................................464 18.4.4 Input Capture Mode ........................................................................................................464 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 18 FlexTimer Module (S08FTMV3) 23 ...
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... Modes of Operation ........................................................................................................487 20.1.4.1 Run Mode .....................................................................................................487 20.1.4.2 Low Power Modes (Wait or Stop) ................................................................487 20.2 External Signals Description .........................................................................................................488 20.3 Memory Map and Register Definition ..........................................................................................488 20.3.1 CRC Data Register (CRCDH1:CRCDH0:CRCDL1:CRCDL0) ....................................488 MC9S08GW64 MCU Series Reference Manual, Rev.3 24 Chapter 19 Chapter 20 Freescale Semiconductor ...
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... Two-Signal Binary Mode ..............................................................................511 21.4.1.4 Two-Signal Gray Mode .................................................................................513 21.4.1.5 Three-Signal Binary Mode ...........................................................................515 21.4.1.6 Three-Signal Gray Mode ..............................................................................517 21.4.1.7 Atomic Counter/PWM Mode (Edge- or Centre-Aligned) ............................519 21.4.2 Noise Filtering ................................................................................................................519 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 21 Position Counter (S08PCNTV1) 25 ...
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... VREF Status and Control Register (VREFSC) ..............................................................544 23.3 Functional Description ..................................................................................................................544 23.3.1 Voltage Reference Disabled, VREFEN=0 ......................................................................545 23.3.2 Voltage Reference Enabled, VREFEN=1 .......................................................................545 23.3.2.1 Mode[1:0]=00 ...............................................................................................545 23.3.2.2 Mode[1:0]=01 ...............................................................................................545 MC9S08GW64 MCU Series Reference Manual, Rev.3 26 Chapter 22 Chapter 23 Voltage Reference (VREFV1) Freescale Semiconductor ...
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... Functional Description ..................................................................................................................571 25.4.1 Comparator .....................................................................................................................571 25.4.1.1 RWA and RWAEN in Full Modes .................................................................571 25.4.2 Breakpoint Control Logic (BCL) ....................................................................................571 25.4.2.1 Breakpoint types ...........................................................................................571 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 24 Development Support Chapter 25 Break Point Unit (BKPT) (64K) 27 ...
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... Full Mode ......................................................................................................572 25.5 Resets ............................................................................................................................................572 25.6 Interrupts .......................................................................................................................................572 MC9S08GW64 MCU Series Reference Manual, Rev.3 28 Freescale Semiconductor ...
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... RAM 1 ADC0 Single-ended Channels ADC0 Differential 2 Channels ADC1 Single-ended Channels ADC1 Differential Channels BKPT ICS IIC IRQ IRTC MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor NOTE MC9S08GW64 80-pin 64-pin LQFP LQFP 65,536 Bytes 4,032 Bytes 7-ch 7- 7-ch 7- yes yes yes ...
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... LQFP LQFP 8-ch 2 yes yes yes yes 2-ch 8x36 8x24 4x40 4x28 yes yes shows the structure of the MC9S08GW64 series MCUs. MC9S08GW32 80-pin 64-pin LQFP LQFP 8-ch 2 yes yes yes yes 2-ch 8x36 8x24 4x40 4x28 yes yes Freescale Semiconductor ...
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... XTAL1 XOSC1 EXTAL1 V BAT TAMPER1 Independent RTC TAMPER2 The RTC separate power domain Figure 1-1. MC9S08GW64 Series Block Diagram MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor PDB Port A: trig[1] trig[1:0] EXTRIG sel[1] sel[1:0] AD[15:2] DADP/M[1] KBI Port B, D: trig[0] KBIP[7:0] ...
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... ICS is configured to use the internal or external reference clock as the reference clock. MC9S08GW64 MCU Series Reference Manual, Rev.3 32 Table 1-2. Module Versions Module (CPU) (ICS) (XOSC) (IRTC) (PCNT) (MTIM8) (MTIM16) (FTM) (PCRC) (PDB) (ADC16) (PRACMP) (LCD) (IIC) (SCI) (SPI) (KBI) (BKPT) (S08ICSV4),” for details on configuring the ICSOUT Version Freescale Semiconductor ...
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... STOP mode. This signal is not available externally. See Converter (ADC16V1),” for details. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor (S08ICSV4)” explains the ICSIRCLK in more detail. (S08ICSV4),” for details. Watchdog” for details on using the LPOCLK (S08ICSV4),” or Chapter 13, “ ...
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... OSCOUT1 MTIMCLK Filter LPO clock MTIM1 PCNT MTIM3 COP MTIM2 (16 bits) (8 bits) SYNC > FFCLK RAM BDM BKPT FLASH OSCOUT1 OSCOUT2 FTMCLK ADACK ADC0 PCRC PDB FTM ADC1 SCI0 SPI0 SCI1 LCD IIC SPI1 SCI2 SPI2 SCI3 Freescale Semiconductor PRACMP 0&1&2 KBI ...
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... Device Pin Assignment This section shows the pin assignments for MC9S08GW64 series devices EXTAL1, XTAL1, TAMPER1, and TAMPER2 pins are in a different BAT power domain. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor NOTE 35 ...
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... SS1 PTG4/CMPOUT1/RxD3/AD10/LCD38 PTG5/CMPOUT2/TxD3/AD11/LCD39 PTG6/CMPP3/AD12/PCNT0/LCD40 PTG7/CMPP4/AD13/PCNT1/LCD41 PTH0/CMPP5/AD14/PCNT2/LCD42 PTH1/RTCCLKOUT/AD15/LCD43 Figure 2-1. MC9S08GW64 Series in 80-Pin LQFP Package MC9S08GW64 MCU Series Reference Manual, Rev LQFP PTC7/PCNTCH1/TxD3/LCD9 59 PTC6/PCNTCH0/RxD3/LCD8 58 PTC5/FTMCH1/TxD1/LCD7 57 PTC4/FTMCH0/RxD1/LCD6 56 PTC3/SS1/LCD5 55 PTC2/SCLK1/LCD4 54 PTC1/MISO1/LCD3 53 PTC0/MOSI1/LCD2 52 PTB7/KBIP7/TxD2/LCD1 51 PTB6/KBIP6/RxD2/LCD0 50 PTB5/KBIP5/SS0/SDA 49 PTB4/KBIP4/SCLK0/SCL 48 PTB3/KBIP3/MISO0/MOSI0/TxD0 47 PTB2/KBIP2/MOSI0/MISO0/RxD0 46 RESET 45 PTB1/KBIP1/RxD1/CMPP6/XTAL2 44 PTB0/KBIP0/TxD1/EXTAL2 PTA6/CMPOUT0/CLKOUT/BKGD/MS Freescale Semiconductor ...
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... PTG1/MISO1/AD7/LCD35 PTG2/SCLK1/AD8/LCD36 PTG3/SS1/AD9/LCD37 PTG4/CMPOUT1/RxD3/AD10/LCD38 PTG5/CMPOUT2/TxD3/AD11/LCD39 PTG6/CMPP3/AD12/PCNT0/LCD40 PTG7/CMPP4/AD13/PCNT1/LCD41 PTH0/CMPP5/AD14/PCNT2/LCD42 PTH1/RTCCLKOUT/AD15/LCD43 Figure 2-2. MC9S08GW64 Series in 64-Pin LQFP Package 2.3 Recommended System Connections Figure 2-3 shows pin connections that are common to MC9S08GW64 series application systems. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor LQFP ...
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... PTC5/FTMCH1/TxD1/LCD7 PTC6/PCNTCH0/RxD3/LCD8 PTC7/PCNTCH1/TxD3/LCD9 PTD0/KBIP0/MOSI2/LCD10 PTD1/KBIP1/MISO2/LCD11 PTD2/KBIP2/SCLK2/LCD12 PTD3/KBIP3/SS2/LCD13 PTD4/KBIP4/LCD14 PTD5/KBIP5/CLKOUT/LCD15 PTD6/KBIP6/LCD16 PTD7/KBIP7/LCD17 PTE0/LCD18 PTE1/LCD19 PTE2/LCD20 PTE3/LCD21 PTE4/LCD22 PTE5/LCD23 PTE6/LCD24 PTE7/LCD25 PTF0/LCD26 PTF1/LCD27 PTF2/LCD28 PTF3/LCD29 PTF4/LCD30 PTF5/LCD31 PTF6/MTIMCLK/AD4/LCD32 PTF7/FTMCLK/AD5/LCD33 PTG0/MOSI1/AD6/LCD34 PTG1/MISO1/AD7/LCD35 PTG2/SCLK1/AD8/LCD36 PTG3/SS1/AD9/LCD37 PTG4/CMPOUT1/RxD3/AD10/LCD38 PTG5/CMPOUT2/TxD3/AD11/LCD39 PTG6/CMPP3/AD12/PCNT0/LCD40 PTG7/CMPP4/AD13/PCNT1/LCD41 PTH0/CMPP5/AD14/PCNT2/LCD42 PTH1/RTCCLKOUT/AD15/LCD43 LCD Glass Freescale Semiconductor ...
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... C and C normally must be high-quality ceramic capacitors that are specifically designed for 1 2 high-frequency applications. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 6 , “Parallel Input/Output and V are available only on the 80-pin LQFP REFH REFL DDA while oscillator2 in the power domain of V BAT (S08ICSV4)” ...
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... Debug Force Reset Register (SBDFR),” for more information), the MC9S08GW64 MCU Series Reference Manual, Rev.3 40 (which are usually the same size first-order approximation, use 2 NOTE level, an external pullup must be used. DD Figure 2-3 for an example and the RESET DD Section 5.8.3, “System Background Freescale Semiconductor 2 ...
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... V interface as shown in Figure As shown in Figure supply. In SPI communication interface, PTB3 must be configued as MOSI0 if serving as a master and be configured as MISO0 if seving as a slaver. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor 2-5. NOTE 2- power supply while V DD Chapter 2 Pins and Connections power ...
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... MC9S08GW64 MCU Series Reference Manual, Rev DD1 /SDA SS0 V DD1 V DD1 Figure 2-4. Connection with 5 V Interface pins are dedicated to providing power to the LCD module. For cap2 Chapter 11, “LCD Module Chapter 11, “LCD Module NOTE V DD1 /SDA SS SCLK/SCL MISO/MOSI/RxD (S08LCDLPV1).” Freescale Semiconductor ...
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... SCI2 is twice the normal I/O drive capability on the Tx pin while SCI1 Tx pin is normal I/O drive capability. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Figure 2-5. Similarly, the Tx outputs of SCI1 and SCI2 can be ...
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... This connection options provide the user more flexibility on using various of sensors. MC9S08GW64 MCU Series Reference Manual, Rev.3 44 Internal or external reference - + analog comparator RX1/2 digital buffer Note1 0 TX1/2 1 SIMIPS2[MODTX1] OR SIMIPS3[MODTX2] Figure 2-5 are discussed in Section 5.8.6, “Internal Peripheral Select opto isolator Note3 opto isolator Off-Chip Opto-Isolators (SIMIPS3).” Freescale Semiconductor ...
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... When a port pin is configured as a general-purpose output or when a peripheral uses the port pin as an output, software can select one of the two drive strengths and enable or disable slew rate control. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Figure 2-6 are discussed in Section 5.8.5, “ ...
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... PTG4 CMPOUT1 RxD3 PTG5 CMPOUT2 TxD3 PTG6 CMPP3 AD12 PTG7 CMPP4 AD13 PTH0 CMPP5 AD14 Alt3 Alt4 AD4 LCD32 AD5 LCD33 AD6 LCD34 AD7 LCD35 AD8 LCD36 AD9 LCD37 AD10 LCD38 AD11 LCD39 PCNT0 LCD40 PCNT1 LCD41 PCNT2 LCD42 Freescale Semiconductor ...
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... PTB6 52 44 PTB7 53 PTC0 54 PTC1 55 PTC2 56 PTC3 57 45 PTC4 58 46 PTC5 59 47 PTC6 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Default func Alt 1 Alt 2 PTH1 RTCCLKOUT AD15 V DDA V REFH V SSA V REFL DADP0 DADM0 V REFO DADP1 DADM1 V BAT EXTAL1 XTAL1 ...
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... KBIP3 PTD4 KBIP4 LCD14 PTD5 KBIP5 CLKOUT PTD6 KBIP6 LCD16 PTD7 KBIP7 LCD17 PTE0 LCD18 PTE1 LCD19 PTE2 LCD20 PTE3 LCD21 PTE4 LCD22 PTE5 LCD23 LL3 V LL2 V LL1 V CAP2 V CAP1 Alt3 Alt4 LCD9 LCD10 LCD11 LCD12 SS2 LCD13 LCD15 Freescale Semiconductor ...
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... Before entering this mode, the following conditions must be met: • FBELP is the selected clock mode for the ICS. • The HGO bit in the ICSC2 register is clear. • The bus frequency is less than 250 kHz. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor 49 ...
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... Section 5.8.3, “System Background Debug Force Reset Register • When a BACKGROUND command is received through the BKGD/MS pin • When a BGND instruction is executed • When encountering a BDC breakpoint • When encountering a BKPT breakpoint MC9S08GW64 MCU Series Reference Manual, Rev.3 50 core. The BDC and (SBDFR).”) Freescale Semiconductor ...
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... MCU is operated in run mode for the first time. When the MC9S08GW64 series are shipped from the Freescale Semiconductor factory, the flash program memory is erased by default unless specifically noted result, no program can be executed in run mode until the flash memory is initially programmed ...
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... SPMSC1 SPMSC2 LVDE LVDSE PPDC x x Stop modes disabled; illegal opcode reset if STOP instruction executed x x Stop3 with BDM enabled Both bits must Stop3 with voltage regulator active Either bit Stop3 Either bit Stop2 Chapter 13, “Internal Clock Stop Mode 2 Freescale Semiconductor ...
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... PPDACK bit. If the peripheral module is not enabled before writing to PPDACK, the pins will be controlled by their associated port control registers when the I/O latches are opened. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor will be near RI levels because internal clocks are enabled. DD ...
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... Exiting stop3 with a reset will put the device back into normal run mode. If LPWUI is clear, interrupts will exit stop3 mode, return the device to low power run mode, and then service the interrupt. If MC9S08GW64 MCU Series Reference Manual, Rev.3 54 Support.” If ENBDM is set when the CPU Freescale Semiconductor Table 3-1. The ...
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... Configured within the ICS module based on the settings of IREFSTEN, EFRESTEN, IRCLKEN and ERCLKEN stop2, CPU, flash, ICS and all peripheral modules are powered down except for LCD. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Table 3-2. Power Mode Selections SPMSC1 SPMSC2 ...
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... Interrupt when LPWUI = 1 LPWAIT NOT SUPPORTED Mode Regulator State RUN Full on WAIT Full on LPRUN Standby LPWAIT Standby STOP3 Standby STOP2 Partial powerdown Table 3-1. RESET Figure 3-1. Figure 3-1. Trigger Table 3-1, switch LPR Table 3-1, issue 1 or PTA5/IRQ, assert an Freescale Semiconductor ...
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... IIC IRQ KBI LVD/LVW MTIMx LCD Optionally On SCIx SPI FTM PDB MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Figure To WAIT WAIT instruction RUN Interrupt or reset Interrupt (if LPR = 0, or LPR = 1 and LPWUI =1) RUN or reset STOP3 STOP instruction Mode,” for specific information on system behavior in stop modes. ...
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... MC9S08GW64 MCU Series Reference Manual, Rev.3 58 Stop2 Stop3 Off Standby Off Optionally On Off Optionally On 10 Optionally Optionally States Held Peripheral Control Section 3.6.4, “LVD Enabled in Stop Mode LPWait LPRun Optionally On Optionally On Optionally On Optionally On Optionally On Optionally On Standby Standby Optionally On Optionally Peripheral Control On Mode”. Freescale Semiconductor ...
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... In GW32, if RAM is accessed beyond 2K boundary then the functionality can not be guaranteed and unexpected behavior will occur. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Table 4-1. System Memory Map Size Name 192 Direct Page Registers 4032 RAM ...
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... Paging Window - PPAGE=0 Extended address- es formed with PPAGE and A13:A0 of CPU ad- 16384 BYTES dress 0xBFFF 0xC000 PPAGE=3 FLASH 16384 BYTES 0xFFFF Figure 4-1. MC9S08GW64 Memory Map PPAGE=7 PPAGE=6 PPAGE=5 PPAGE=4 FLASH 16384 BYTES PPAGE=3 PPAGE=2 PPAGE=1 FLASH Freescale Semiconductor ...
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... Reset and Interrupt Vector Assignments Table 4-2 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale Semiconductor provided equate file for the MC9S08GW64 series. Address (High/Low) 0xFF80:FF81 0xFF94:FF95 ...
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... SCI0 Error LVD IRQ SWI RESET V KBI V PCNT V PRCMP2 V PRCMP1 V PRCMP0 V ADC1 V ADC0 V MTIM2 V MTIM1 V MTIM0 V FTMOF V FTMCH0 V FTMCH1 V IIC V SPI2 V SPI1 V SPI0 V SCI3TX V SCI3RX V SCI3ERR V SCI2TX V SCI2RX V SCI2ERR V SCI1TX V SCI1RX V SCI1ERR V SCI0TX V SCI0RX V SCI0ERR V LVD V IRQ V SWI V RESET Freescale Semiconductor ...
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... Shaded cells with dashes indicate unused or reserved bit locations that could read 0s. When writing to these bits, write a 0 unless otherwise specified. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor can use the more efficient direct addressing mode, which requires 4-6, the whole address in column one is shown in bold. In ...
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... PTGDD1 — — PTHD1 — — PTHDD1 COUNT MOD COUNT MOD CNTH CNTL MODH MODL — — — TRIGSEL IE MOD[15:8] MOD[7:0] Freescale Semiconductor 1 Bit 0 PTAD0 PTADD0 PTBD0 PTBDD0 PTCD0 PTCDD0 PTDD0 PTDDD0 PTED0 PTEDD0 PTFD0 PTFDD0 PTGD0 PTGDD0 PTHD0 PTHDD0 — ...
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... ADC0RHB 0x0047 ADC0RLB 0x0048 SPI0C1 SPIE 0x0049 SPI0C2 0 0x004A SPI0BR 0 0x004B SPI0S SPRF 0x004C Reserved — 0x004D SPI0D Bit 7 0x004E- Reserved — 0x004F Freescale Semiconductor ERRB AOS DELAY[15:8] DELAY[7:0] DELAY[15:8] DELAY[7:0] RESERVED RESERVED ERRB AOS DELAY[15:8] DELAY[7:0] DELAY[15:8] DELAY[7:0] — — ...
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... CURR_INV 0 SINVF RCOVF MODE CHANNEL_SEL FILTER VALUE CURR_STATE KBF KBACK KBIE KBIPE3 KBIPE2 KBIPE1 KBEDG3 KBEDG2 KBEDG1 IRQF IRQACK IRQIE Freescale Semiconductor Bit 0 LSBFE SPC0 SPR0 0 — Bit 0 — LSBFE SPC0 SPR0 0 — Bit 0 — FCOVF 0 KBIMOD KBIPE0 KBEDG0 IRQMOD ...
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... IICSMB FACK 0x0098 IICA2 SAD7 0x0099 IICSLTH SSLT15 0x009A IICSLTL SSLT7 0x009B- Reserved — 0x009F 0x00A0 FTMSC TOF 0x00A1 FTMCNTH Bit 15 0x00A2 FTMCNTL Bit 7 Freescale Semiconductor RXEDGIE 0 SBR12 SBR6 SBR5 SBR4 SCISWAI RSRC M TCIE RIE ILIE TC RDRF IDLE RXEDGIF 0 RXINV T8 TXDIR ...
Page 68
... BPEN3 BPEN2 BPEN1 BPEN11 BPEN10 BPEN9 BPEN19 BPEN18 BPEN17 BPEN27 BPEN26 BPEN25 BPEN35 BPEN34 BPEN33 BPEN43 BPEN42 BPEN41 Freescale Semiconductor Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — CRCW — Bit 0 PEN0 PEN8 PEN16 PEN24 PEN32 PEN40 — ...
Page 69
... LCDWF34 BPHLCD34 BPGLCD34 BPFLCD34 BPELCD34 BPDLCD34 BPCLCD34 BPBLCD34 BPALCD34 0x10B3 LCDWF35 BPHLCD35 BPGLCD35 BPFLCD35 BPELCD35 BPDLCD35 BPCLCD35 BPBLCD35 BPALCD35 0x10B4 LCDWF36 BPHLCD36 BPGLCD36 BPFLCD36 BPELCD36 BPDLCD36 BPCLCD36 BPBLCD36 BPALCD36 Freescale Semiconductor Table 4-4. LCD Registers (Sheet — — — — ...
Page 70
... MODTX1 MTBASE2 DDRIVE MODTX2 — — — CS ICS_EXT_ CLK_SEL — — — LVDSE LVDE BGBDS PPDF PPDACK PPDE Freescale Semiconductor Bit 0 — — Bit 0 0 BDFR COPW — — ID8 ID0 — SCI0 SPI0 PTA MTIM3 FLS 0 — — BGBE PPDC ...
Page 71
... ADC0CV1L 0x1842 ADC0CV2H 0x1843 ADC0CV2L 0x1844 ADC0SC2 ADACT 0x1845 ADC0SC3 CAL 0x1846 ADC0OFSH 0x1847 ADC0OFSL 0x1848 ADC0PGH 0x1849 ADC0PGL MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor — — — LVWACK LVDV LVWV PRDIV8 FNORED 0 0 — — — 0 KEYACC 0 FPS ...
Page 72
... SBR11 SBR10 SBR9 SBR3 SBR2 SBR1 WAKE ILT RWU RWUID BRK13 LBKDE ORIE NEIE FEIE SBR11 SBR10 SBR9 SBR3 SBR2 SBR1 WAKE ILT PE Freescale Semiconductor Bit 0 — — Bit 8 Bit 0 — SBR8 SBR0 PT SBK PF RAF PEIE Bit 0 SBR8 SBR0 PT ...
Page 73
... IRTC_CTRL 0 0x1891 0 0x1892 IRTC_STATUS 0 0x1893 0 0x1894 IRTC_ISR SAM7 0x1895 2Hz 0x1896 IRTC_IER SAM7 0x1897 2Hz 0x1898 IRTC_COUNT_DN 0 0x1899 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor TCIE RIE ILIE TC RDRF IDLE RXEDGIF 0 RXINV T8 TXDIR TXINV SOURCE LCLK2 LCLK1 HREFSEL LADJ1 ...
Page 74
... MSB LSB MSB LSB MSB LSB Bit 0 — — — — DST_START_HOUR DST_END_HOUR DST_START_MONTH DST_END_MONTH DST_START_DAY DST_END_DAY TIME STAMP MONTHS TIME STAMP DAY TIME STAMP HOURS TAMPER2 TAMPER1 BAT_RAMPER TAMPER2_C TAMPER1_C BAT_RAMPE 0 TRL TRL R_CTRL — — — — Freescale Semiconductor ...
Page 75
... PTAIFE 0 0x18E4 PTBPE PTBPE7 0x18E5 PTBSE PTBSE7 0x18E6 PTBDS PTBDS7 0x18E7 PTBIFE PTBIFE7 0x18E8 PTCPE PTCPE7 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB ...
Page 76
... PTGPE2 PTGPE1 PTGPE0 PTGSE2 PTGSE1 PTGSE0 PTGDS2 PTGDS1 PTGDS0 PTGIFE2 PTGIFE1 PTGIFE0 — — PTHPE1 PTHPE0 — — PTHSE1 PTHSE0 — — PTHDS1 PTHDS0 — — PTHIFE1 PTHIFE0 ACREN 0 REFSEL ADCO AVGE AVGS CLPD CLPS 0 0 CLP4[9: CLP3[8] Freescale Semiconductor Bit 0 ...
Page 77
... VREFTRM 0x1931 VREFSC VREFEN 0x1932- Reserved — 0x193F 0x1940 PTAPF1 0 0x1941 PTAPF2 0 0x1942 PTAPF3 0 0x1943 PTAPF4 0 0x1944 PTBPF1 0 0x1945 PTBPF2 0 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor CLP3[7:0] CLP2 0 — — — CLM4[7: CLM3[7:0] CLM2 0 ADPC6 ADPC5 ADPC4 ADPC3 ADPC14 ...
Page 78
... The internal reference trim values stored in flash, TRIM and FTRIM, can be programmed by third party programmers and must be copied into the corresponding ICS registers by user code to override the factory trim. MC9S08GW64 MCU Series Reference Manual, Rev Table 4-6, are used for storing values used by several 2 1 Bit Freescale Semiconductor ...
Page 79
... Extended program space using paging scheme — PPAGE register used for page selection — fixed 16 KB memory window — architecture supports up to 256 pages each • Extended data space using linear address pointer MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor VREF TRIM 0 0 ...
Page 80
... The contents of LAP2:LAP0 will auto-increment when accessing data using the LBP and LWP registers. The contents of LAP2:LAP0 can be increased by writing an 8-bit value to LAPAB. MC9S08GW64 MCU Series Reference Manual, Rev Figure 4-3. Program Page Register (PPAGE) Description XA16 XA15 Freescale Semiconductor 0 XA14 0 ...
Page 81
... Linear Byte Post Increment Register (LBP) This register is one of three data registers that the user can use to access any flash memory location in the extended address map. When LBP is accessed, the contents of LAP2:LAP0 make up the extended address MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor ...
Page 82
... Linear Address Pointer Add Byte Register (LAPAB) The user can increase or decrease the contents of LAP2:LAP0 by writing a 2s compliment value to LAPAB. The value written is added to the current contents of LAP2:LAP0. MC9S08GW64 MCU Series Reference Manual, Rev Description Figure 4-7. Linear Byte Register (LB) Description Freescale Semiconductor ...
Page 83
... CALL is similar to a JSR instruction, but the subroutine that it called can be located anywhere in the normal 64 KB address space or on any page of program memory. During the execution of a CALL instruction, the CPU: • Stacks the return address. • Pushes the current PPAGE value onto the stack. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor ...
Page 84
... MMU to add that value to the existing value in LAP2:LAP0. 4.5.3.1.4 PPAGE and Linear Address Pointer to Extended Address See Figure 4-1 or Figure 4-2, on how the program PPAGE memory pages and the linear address pointer are mapped to extended address space. MC9S08GW64 MCU Series Reference Manual, Rev.3 84 Freescale Semiconductor ...
Page 85
... MC9S08GW64 series usually best to reinitialize the stack pointer to the top of the RAM so the direct-page RAM can be used for frequently accessed RAM variables and bit-addressable program variables. Include the following 2-instruction sequence in your reset initialization routine (where RamLast is equated to the highest address of the RAM in the Freescale Semiconductor-provided equate file). LDHX #RamLast+1 ...
Page 86
... Table 4-13. Program and Erase Times Cycles of FCLK 9 4 4000 20,000 NOTE ) between 150 kHz and 200 kHz FCLK ) is used by the command FCLK . The times are shown as a number = 5 s. Program and erase times Time if FCLK = 200 kHz 45 s 20 100 ms Freescale Semiconductor ...
Page 87
... Figure 4-9 programming. The FCDIV register must be initialized before using any flash commands. This must be done only once following a reset. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor is a flowchart for executing all of the commands except for burst Chapter 4 Memory 87 ...
Page 88
... CLEAR ERRORS WRITE TO FLASH OR EEPROM TO BUFFER ADDRESS AND DATA WRITE COMMAND TO FCMD WRITE 1 TO FCBEF (2) Wait at least four bus cycles before checking FCBEF or FCCF. TO LAUNCH COMMAND (2) AND CLEAR FCBEF YES FPVIOL OR FACCERR (3) FCCF? 1 DONE Required only once ERROR EXIT Freescale Semiconductor ...
Page 89
... FACCERR error. Such as executing a STOP instruction or writing to the flash. Reads of the flash during program or erase are ignored and invalid data is returned. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor (1) WRITE TO FCDIV START FACCERR OR FPVIOL? 1 CLEAR ERRORS FCBEF? 1 WRITE TO Flash ...
Page 90
... This address is formed by concatenating FPS7:FPS1 with logic 1 bits as shown. For example, to protect the last 1536 bytes of memory (addresses 0xFA00 through 0xFFFF), MC9S08GW64 MCU Series Reference Manual, Rev.3 90 NVPROT)”). Figure 4-11. The FPS bits are used as the upper bits of Section 4.9.4, “Flash Freescale Semiconductor ...
Page 91
... Security is engaged or disengaged based on the state of two nonvolatile register bits (SEC01:SEC00) in the FOPT register. During reset, the contents of the nonvolatile location NVOPT are copied from flash into the working FOPT register in high-page register space. A user engages security by programming the MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor 1 A12 A11 ...
Page 92
... Mass erase flash if necessary. 3. Blank check flash. Provided flash is completely erased, security is disengaged until the next reset. To avoid returning to secure mode after the next reset, program NVOPT so SEC01:SEC00 = 1:0. MC9S08GW64 MCU Series Reference Manual, Rev.3 92 Freescale Semiconductor ...
Page 93
... Table 4-6 for the absolute address assignments for all flash registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file is normally used to translate these names into the appropriate absolute addresses. 4.9.1 Flash Clock Divider Register (FCDIV) Bit 7 of this register is a read-only flag ...
Page 94
... Figure 4-13. Flash Options Register (FOPT) Description Section 4.8, Section 4.8, Program/Erase Timing Pulse (5 s Min, 6.7s Max) 5.2 s 5 s 5 s 5 s 5 s 5 s 5 s 6.7 SEC01 “Security.” Table “Security.” Freescale Semiconductor 0 SEC00 4-17. When ...
Page 95
... This register is loaded from nonvolatile location NVPROT during reset. 1 Background commands can be used to change the contents of these bits in FPROT. Figure 4-15. Flash Protection Register (FPROT) MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Table 4-17. Security States SEC01:SEC00 Description 0:0 secure ...
Page 96
... FPVIOL is cleared by writing FPVIOL protection violation attempt was made to erase or program a protected location. MC9S08GW64 MCU Series Reference Manual, Rev.3 96 Description 5 4 FPVIOL FACCERR 0 0 Figure 4-16. Flash Status Register (FSTAT) Description FBLANK Freescale Semiconductor ...
Page 97
... All other command codes are illegal and generate an access error not necessary to perform a blank check command after a mass erase operation. Blank check is required as part of the security unlocking mechanism. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Description Section 4.7.5, “Access Execution,” for a detailed discussion of flash programming and erase ...
Page 98
... Chapter 4 Memory MC9S08GW64 MCU Series Reference Manual, Rev.3 98 Freescale Semiconductor ...
Page 99
... External pin reset (PIN) • Computer operating properly (COP) timer • Illegal opcode detect (ILOP) • Illegal address detect (ILAD) • Low-voltage detect (LVD) • Background debug forced reset MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor NOTE Table 5-2) 99 ...
Page 100
... MC9S08GW64 MCU Series Reference Manual, Rev.3 100 Section 5.8.4, “System Options Register 1 Section 5.8.4, “System Options Register 1 Table 5-1 summaries the control functions of the COPCLKS and (SOPT1), ” for additional Freescale Semiconductor ...
Page 101
... ISR (after clearing the status flag that generated the interrupt) so that other interrupts can be serviced without waiting for the first service routine to finish. This practice is not MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Table 5-1. COP Configuration Options ...
Page 102
... CONDITION CODE REGISTER 4 2 ACCUMULATOR * 3 3 INDEX REGISTER (LOW BYTE PROGRAM COUNTER HIGH 1 5 PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame 0 SP AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...
Page 103
... IRQF status flag becomes set when an edge is detected (when the IRQ pin changes from the deasserted to the asserted level), but the flag is continuously set (and cannot be cleared) as long as the IRQ pin remains at the asserted level. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control 103 ...
Page 104
... CCR the CPU will finish the current instruction; stack the PCL, PCH and CCR CPU registers; set the I bit; and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. MC9S08GW64 MCU Series Reference Manual, Rev.3 104 Freescale Semiconductor ...
Page 105
... Highest MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Table 5-2. Interrupt Vectors Vector Name Module Source Unused Vector Space (available for user program) Vpdb PDB IF Vpdberr PDB ...
Page 106
... Using this system, the user can enable or disable the bus clock to each of the peripherals at the clock source, eliminating unnecessary clocks to peripherals which are not in use and thereby reducing the overall run and wait mode currents. MC9S08GW64 MCU Series Reference Manual, Rev.3 106 ) and one low (V ). The trip voltage is selected LVWH LVWL ) LVDH Freescale Semiconductor ...
Page 107
... R 0 IRQPDD W Reset Unimplemented or Reserved Figure 5-2. Interrupt Request Status and Control Register (IRQSC) MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control NOTE in Chapter 4 , “Memory,” of this manual for the absolute address IRQF IRQEDG ...
Page 108
... See Section 5.5.2.2, “Edge and Level 0 IRQ event on falling edges or rising edges only. 1 IRQ event on falling edges and low levels or on rising edges and high levels. MC9S08GW64 MCU Series Reference Manual, Rev.3 108 Description Sensitivity” for more details. Freescale Semiconductor ...
Page 109
... STOPE = 0 in the SOPT register. The BGND instruction is considered illegal if active background mode is disabled by ENBDM = 0 in the BDCSC register. 0 Reset not caused by an illegal opcode. 1 Reset caused by an illegal opcode. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control 5 4 COP ...
Page 110
... PTC6/ACMPO/BKGD/MS must be high immediately after issuing WRITE_BYTE command. To enter BDM, PTC6/ACMPO/BKGD/MS must be low immediately after issuing WRITE_BYTE command. See the data sheet for more information. MC9S08GW64 MCU Series Reference Manual, Rev.3 110 Description Description BDFR Freescale Semiconductor ...
Page 111
... SRS register must occur in the last 25% of the selected period. Any write to the SRS register during the first 75% of the selected period will reset the MCU. 0 Normal COP operation. 1 Window COP operation. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control ...
Page 112
... To select the pin input coming as digital select the pin input coming to go through PRACMPx to be converted into Digital 2 MTIM2 External Clock Select — MTIM2CS 0 = MTIMCLK 1 = TOF of MTIM1 MC9S08GW64 MCU Series Reference Manual, Rev.3 112 MTIM3CS PCNTSS Description Figure 2-6 for an illustration MTIM2CS Freescale Semiconductor ...
Page 113
... Reserved 0 Modulate TxD1 — MODTX1 not modulate the output of SCI1 1 = Modulate the output of SCI1 with the timebase selected via the MTBASE1 field MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Figure 2 RX1IN MTBASE1 ...
Page 114
... Do not modulate the output of SCI2 1 = Modulate the output of SCI2 with the timebase selected via the MTBASE2 field MC9S08GW64 MCU Series Reference Manual, Rev.3 114 Figure 2 RX2IN MTBASE2 Table 5-9. SIMIPS3 Register Bit Fields Description for an illustration of these controls DDRIVE MODTX2 0 0 Freescale Semiconductor 0 0 ...
Page 115
... OSCOUT1 0010 = OSCOUT2 0011 = Internal oscillator 0100 = BUSCLK 0101 = Core Clock 0110 = LPOCLK 1000 = ADC0 asynchronous clock 1001 = ADC1 asynchronous clock Rest options are reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Table 5-10 ...
Page 116
... XOSC1 is selected as the external clock input to the ICS Note: This bit should only be changed when the ICS is NOT utilizing the external clock input. MC9S08GW64 MCU Series Reference Manual, Rev.3 116 Table 5-11. CCSCTRL Register Bit Fields Description ICS_EXT_CL K_SEL Freescale Semiconductor ...
Page 117
... Figure 5-12. CLKOUT Prescaler Register (CLK_PRSC_L) Table 5-13. CLK_PRSC_L Register Bit Fields Field 7–0 Bit 7–Bit 0: CLKOUT Prescaler match value bit 7 to bit 0 Bit 7–Bit 0 MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control ...
Page 118
... Part Identification Number — Each derivative in the HCS08 family has a unique identification number. The ID[7:0] MC9S08GW64 is hard coded to the value 0x030.See also ID bits in MC9S08GW64 MCU Series Reference Manual, Rev.3 118 ID11 — — 0 Description ID5 ID4 ID3 Description ID10 ID9 ID8 Table 5-15 ID2 ID1 ID0 Table 5-14 Freescale Semiconductor ...
Page 119
... Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation LVDE of other bits in this register. 0 LVD logic disabled. 1 LVD logic enabled. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control ...
Page 120
... The voltage regulator will exit standby on an interrupt. MC9S08GW64 MCU Series Reference Manual, Rev.3 120 Description Section 3.3.1, “Low-Power Run Mode (LPWait),” and PPDF LPWUI Description Section 3.6, “Stop Modes,” for more PPDE PPDC PPDACK Unaffected by reset Freescale Semiconductor ...
Page 121
... LVWACK clears LVWF low voltage warning is not present. 5 Low-Voltage Detect Voltage Select — The LVDV bit indicates the LVD trip point voltage (V LVDV 0 Low trip point selected (V 1 High trip point selected (V MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Description LVDV LVWV ...
Page 122
... MC9S08GW64 MCU Series Reference Manual, Rev.3 122 Description = V ). LVW LVWL = V ). LVW LVWH LVW Trip Point V = 2.16 V LVWL V = 2.46 V LVWH V = 2.16 V LVWL V = 2.46 V LVWH Gating,” for more information. NOTE KBI IIC SCI3 LVW 1 LVD Trip Point V = 1.82 V LVDL V = 2.16 V LVDH SCI2 SCI1 SCI0 Freescale Semiconductor ...
Page 123
... User software must disable the peripheral before disabling the clocks to the peripheral. When clocks are re-enabled to a peripheral, the peripheral registers need to be re-initialized by user software. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Description Section 5.8.10, “CLKOUT Prescaler Register Section 5.7, “ ...
Page 124
... SPI0 Clock Gate Control — This bit controls the clock gate to the SPI0 module. SPI0 0 Bus clock to the SPI0 module is disabled. 1 Bus clock to the SPI0 module is enabled. MC9S08GW64 MCU Series Reference Manual, Rev.3 124 VREF IRQ LCD Description SPI2 SPI1 SPI0 Freescale Semiconductor ...
Page 125
... PTA Clock Gate Control — This bit controls the clock gate to the PTA module. PTA 0 Bus clock to the PTA module is disabled. 1 Bus clock to the PTAmodule is enabled. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control NOTE 5 4 ...
Page 126
... MTIM3 Clock Gate Control — This bit controls the bus clock gate to the MTIM3 module. MTIM3 0 Bus clock to the MTIM3 module is disabled. 1 Bus clock to the MTIM3 module is enabled. MC9S08GW64 MCU Series Reference Manual, Rev.3 126 Gating,” for more information. NOTE CRC FTM PDB Description MTIM1 MTIM2 MTIM3 Freescale Semiconductor ...
Page 127
... FLASH Clock Gate Control — This bit controls the bus clock gate to the FLASH module. FLS 0 Bus clock to the FLASH module is disabled. 1 Bus clock to the FLASH module is enabled. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Gating,” for more information. NOTE 5 ...
Page 128
... Chapter 5 Resets, Interrupts, and General System Control MC9S08GW64 MCU Series Reference Manual, Rev.3 128 Freescale Semiconductor ...
Page 129
... The input buffer for the associated pin is always enabled unless the pin is enabled as an analog function output-only pin. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Connections,” for more information about pin assignments and external Table 2-1 ...
Page 130
... The pullup device is disabled if the pin is controlled by an analog function or any shared peripheral function regardless of the state of the corresponding pullup enable register bit. MC9S08GW64 MCU Series Reference Manual, Rev.3 130 PTxDDn D Q PTxDn Figure 6-1. Parallel I/O Block Diagram Output Enable Output Data Input Data Synchronizer Freescale Semiconductor ...
Page 131
... If the LCD module is configured to operate in stop modes, the drive mode of the GPIO shared with LCD will be retained upon stop recovery. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Chapter 6 Parallel Input/Output Control externally, VSUPPLY = 11, FCDEN DD 131 ...
Page 132
... MHz to 30 MHz bandwidth) is enabled in the logic input path. When cleared, the filter is bypassed. Table 6-1 shows the fixed control signals for some dedicated pins. Table 6-1. Fixed Control Signal for Some Pins RESET TAMPER1/2 BKGD/MS MC9S08GW64 MCU Series Reference Manual, Rev.3 132 IFE Freescale Semiconductor ...
Page 133
... MCU pin. Reset forces PTAD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures all port pins as high-impedance inputs with pullups/pulldowns disabled. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor PE SE From IRQ ...
Page 134
... PTAD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port A bit n and PTAD reads return the contents of PTADn. MC9S08GW64 MCU Series Reference Manual, Rev.3 134 PTADD5 PTADD4 PTADD3 Description PTADD2 PTADD1 PTADD0 Freescale Semiconductor ...
Page 135
... PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor ...
Page 136
... Port A Input Filter Enable — Input low-pass filter enable control bits for PTA pins. PTAIFE[5:0] 0 Input filter disabled 1 Input filter enabled MC9S08GW64 MCU Series Reference Manual, Rev.3 136 PTADS5 PTADS4 PTADS3 Description PTAIFE5 PTAIFE4 PTAIFE3 Table 6-7. PTAIFE Field Descriptions Description PTADS2 PTADS1 PTADS0 PTAIFE2 PTAIFE1 PTAIFE0 Freescale Semiconductor ...
Page 137
... Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for PTBDD[7:0] PTBD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor 5 4 PTBD5 PTBD4 PTBD3 ...
Page 138
... PTB pin. For port B pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port B bit n. 1 Output slew rate control enabled for port B bit n. MC9S08GW64 MCU Series Reference Manual, Rev.3 138 PTBPE5 PTBPE4 PTBPE3 Description PTBSE5 PTBSE4 PTBSE3 Description PTBPE2 PTBPE1 PTBPE0 PTBSE2 PTBSE1 PTBSE0 Freescale Semiconductor ...
Page 139
... Figure 6-13. Port B Input Filter Enable Register (PTBIFE) Field 7:0 Port B Input Filter Enable — Input low-pass filter enable control bits for PTB pins. PTBIFE[7:0] 0 Input filter disabled 1 Input filter enabled MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor PTBDS5 PTBDS4 PTBDS3 0 ...
Page 140
... Output driver enabled for port C bit n and PTCD reads return the contents of PTCDn. MC9S08GW64 MCU Series Reference Manual, Rev.3 140 PTCD5 PTCD4 PTCD3 Figure 6-14. Port C Data Register (PTCD) Description PTCDD5 PTCDD4 PTCDD3 Description PTCD2 PTCD1 PTCD0 PTCDD2 PTCDD1 PTCDD0 Freescale Semiconductor ...
Page 141
... PTC pin. For port C pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port C bit n. 1 Output slew rate control enabled for port C bit n. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor ...
Page 142
... Port C Input Filter Enable — Input low-pass filter enable control bits for PTC pins. PTCIFE[7:0] 0 Input filter disabled 1 Input filter enabled MC9S08GW64 MCU Series Reference Manual, Rev.3 142 PTCDS5 PTCDS4 PTCDS3 Description PTCIFE5 PTCIFE4 PTCIFE3 Table 6-19. PTCIFE Field Descriptions Description PTCDS2 PTCDS1 PTCDS0 PTCIFE2 PTCIFE1 PTCIFE0 Freescale Semiconductor ...
Page 143
... Data Direction for Port D Bits — These read/write bits control the direction of port D pins and what is read for PTDDD[7:0] PTDD reads. 0 Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for port D bit n and PTDD reads return the contents of PTDDn. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor PTDD5 PTDD4 ...
Page 144
... PTD pin. 0 Output slew rate control disabled for port D bit n. 1 Output slew rate control enabled for port D bit n. MC9S08GW64 MCU Series Reference Manual, Rev.3 144 PTDPE5 PTDPE4 PTDPE3 Description PTDSE5 PTDSE4 PTDSE3 Description PTDPE2 PTDPE1 PTDPE0 PTDSE2 PTDSE1 PTDSE0 Freescale Semiconductor ...
Page 145
... Figure 6-25. Port D Input Filter Enable Register (PTDIFE) Field 7:0 Port D Input Filter Enable — Input low-pass filter enable control bits for PTD pins. PTDIFE[7:0] 0 Input filter disabled 1 Input filter enabled MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor PTDDS5 PTDDS4 PTDDS3 0 ...
Page 146
... Output driver enabled for Port E bit n and PTED reads return the contents of PTEDn. MC9S08GW64 MCU Series Reference Manual, Rev.3 146 PTED5 PTED4 PTED3 Figure 6-26. Port E Data Register (PTED) Description PTEDD5 PTEDD4 PTEDD3 Description PTED2 PTED1 PTED0 PTEDD2 PTEDD1 PTEDD0 Freescale Semiconductor ...
Page 147
... Output slew rate control disabled for port E bit n. 1 Output slew rate control enabled for port E bit n. 6.6.5.5 Port E Input Filter Enable Register (PTEIFE PTEIFE7 PTEIFE6 W Reset Figure 6-30. Port E Input Filter Enable Register (PTEIFE) MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor PTEPE5 PTEPE4 PTEPE3 Description PTESE5 ...
Page 148
... Output driver enabled for Port F bit n and PTFD reads return the contents of PTFDn. MC9S08GW64 MCU Series Reference Manual, Rev.3 148 Table 6-30. PTEIFE Field Descriptions Description PTFD5 PTFD4 PTFD3 Figure 6-31. Port F Data Register (PTFD) Description PTFDD5 PTFDD4 PTFDD3 Description PTFD2 PTFD1 PTFD0 PTFDD2 PTFDD1 PTFDD0 Freescale Semiconductor ...
Page 149
... Output slew rate control disabled for port F bit n. 1 Output slew rate control enabled for port F bit n. 6.6.6.5 Port F Input Filter Enable Register (PTFIFE PTFIFE7 PTFIFE6 W Reset Figure 6-35. Port F Input Filter Enable Register (PTFIFE) MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor PTFPE5 PTFPE4 PTFPE3 Description PTFSE5 ...
Page 150
... Output driver enabled for Port G bit n and PTGD reads return the contents of PTGDn. MC9S08GW64 MCU Series Reference Manual, Rev.3 150 Table 6-35. PTFIFE Field Descriptions Description PTGD5 PTGD4 PTGD3 Figure 6-36. Port G Data Register (PTGD) Description PTGDD5 PTGDD4 PTGDD3 Description PTGD2 PTGD1 PTGD0 PTGDD2 PTGDD1 PTGDD0 Freescale Semiconductor ...
Page 151
... Output slew rate control disabled for port G bit n. 1 Output slew rate control enabled for port G bit n. 6.6.7.5 Port G Input Filter Enable Register (PTGIFE PTGIFE7 PTGIFE6 W Reset Figure 6-40. Port G Input Filter Enable Register (PTGIFE) MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor PTGPE5 PTGPE4 PTGPE3 Description PTGSE5 ...
Page 152
... Input (output driver disabled) and reads return the pin value. 1 Output driver enabled for Port H bit n and PTHD reads return the contents of PTHDn. MC9S08GW64 MCU Series Reference Manual, Rev.3 152 Table 6-40. PTGIFE Field Descriptions Description Figure 6-41. Port H Data Register (PTHD) Description Description PTHD1 PTHD0 PTHDD1 PTHDD0 Freescale Semiconductor ...
Page 153
... Output slew rate control disabled for port H bit n. 1 Output slew rate control enabled for port H bit n. 6.6.8.5 Port H Input Filter Enable Register (PTHIFE Reset Figure 6-45. Port H Input Filter Enable Register (PTHIFE) MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Description ...
Page 154
... PTDPF1 0x194D PTDPF2 0x194E PTDPF3 0x194F PTDPF4 0x1950 PTEPF1 MC9S08GW64 MCU Series Reference Manual, Rev.3 154 Table 6-45. PTHIFE Field Descriptions Description Table 2-1. That is, default functions are assigned value Table 6-46. Pin Mux Control Registers Bit Bit Freescale Semiconductor ...
Page 155
... Configuring the mux control registers to the ADC pins disables the digital function of the pin to ensure proper ADC conversion. The port must not be configured as reserved functions, it may cause pin damage. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Parallel Input/Output ControlChapter 6 Parallel Input/Output Control Table 6-46. Pin Mux Control Registers 0 E3 ...
Page 156
... MISO2 010 PCNT1 011 SDA 100 AD3 101–111Reserved 2–0 Port A0 Pin Mux Controls. A0 000 PTA0 001 MOSI2 010 PCNTCH0 011 SCL 100 AD2 101–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 156 Table 6-47. PTAPF1 Field Descriptions Description Freescale Semiconductor ...
Page 157
... CMMP1 101 ~ 111Reserved 2–0 Port A2 Pin Mux Controls. A2 000 PTA2 001 SCLK2 010 FTMCH0 011 PCNT0 100 CMPP0 101–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Parallel Input/Output ControlChapter 6 Parallel Input/Output Control Table 6-48. PTAPF2 Field Descriptions Description ...
Page 158
... Figure 6-49. Port A Pin Function Register 4 (PTAPF4) Field 2–0 Port A6 Pin Mux Controls. A6 000 PTA6 001 CMPOUT0 010 CLKOUT 011 BKGD/MS 100–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 158 Table 6-49. PTAPF3 Field Descriptions Description Table 6-50. PTAPF4 Field Descriptions Description Freescale Semiconductor ...
Page 159
... CMPP6 100 XTAL2 101 –111Reserved 2–0 Port B0 Pin Mux Controls. B0 000 PTB0 001 KBIP0 010 TxD1 011 EXTAL2 100–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Parallel Input/Output ControlChapter 6 Parallel Input/Output Control Table 6-51. PTBPF1 Field Descriptions Description ...
Page 160
... KBIP3 010 MISO0 011 MOSI0 100 TxD0 101–111Reserved 2–0 Port B2 Pin Mux Controls. B2 000 PTB2 001 KBIP2 010 MOSI0 011 MISO0 100 RxD0 101–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 160 Table 6-52. PTBPF2 Field Descriptions Description Freescale Semiconductor ...
Page 161
... TxD2 011 LCD1 100–111Reserved 2–0 Port B6 Pin Mux Controls. B6 000 PTB6 001 KBIP6 010 RxD2 011 LCD0 100–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Parallel Input/Output ControlChapter 6 Parallel Input/Output Control Table 6-53. PTBPF3 Field Descriptions Description ...
Page 162
... PTC3 001 SS1 010 LCD5 011–111Reserved 2–0 Port C2 Pin Mux Controls. C2 000 PTC2 001 SCLK1 010 LCD4 011–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 162 Table 6-55. PTCPF1 Field Descriptions Description Table 6-56. PTCPF2 Field Descriptions Description Freescale Semiconductor ...
Page 163
... TxD3 011 LCD9 100–111Reserved 2–0 Port C6 Pin Mux Controls. C6 000 PTC6 001 PCNTCH0 010 RxD3 011 LCD8 100–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Parallel Input/Output ControlChapter 6 Parallel Input/Output Control Table 6-57. PTCPF3 Field Descriptions Description ...
Page 164
... SS2 011 LCD13 100 –111Reserved 2–0 Port D2 Pin Mux Controls. D2 000 PTD2 001 KBIP2 010 SCLK2 011 LCD12 100–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 164 Table 6-59. PTDPF1 Field Descriptions Description Table 6-60. PTDPF2 Field Descriptions Description Freescale Semiconductor ...
Page 165
... PTD7 001 KBIP7 010 LCD17 011–111Reserved 2–0 Port D6 Pin Mux Controls. D6 000 PTD6 001 KBIP6 010 LCD16 011–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Parallel Input/Output ControlChapter 6 Parallel Input/Output Control Table 6-61. PTDPF3 Field Descriptions Description ...
Page 166
... Port E3 Pin Mux Controls. E3 000 PTE3 001 LCD21 010–111 Reserved 2–0 Port E2 Pin Mux Controls. E2 000 PTE2 001 LCD20 010–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 166 Table 6-63. PTEPF1 Field Descriptions Description Table 6-64. PTEPF2 Field Descriptions Description Freescale Semiconductor ...
Page 167
... PTE7 001 Reserved 010 LCD25 011–111Reserved 2–0 Port E6 Pin Mux Controls. E6 000 PTE6 001 Reserved 010 LCD24 011–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Parallel Input/Output ControlChapter 6 Parallel Input/Output Control Table 6-65. PTEPF3 Field Descriptions Description ...
Page 168
... Port F3 Pin Mux Controls. F3 000 PTF3 001 LCD29 010–111Reserved 2–0 Port F2 Pin Mux Controls. F2 000 PTF2 001 LCD28 010–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 168 Table 6-67. PTFPF1 Field Descriptions Description Table 6-68. PTFPF2 Field Descriptions Description Freescale Semiconductor ...
Page 169
... AD5 011 LCD33 100–111Reserved 2–0 Port F6 Pin Mux Controls. F6 000 PTF6 001 MTIMCLK 010 AD4 011 LCD32 100–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Parallel Input/Output ControlChapter 6 Parallel Input/Output Control Table 6-69. PTFPF3 Field Descriptions Description ...
Page 170
... AD9 011 LCD37 100–1111Reserved 2–0 Port G2 Pin Mux Controls. G2 000 PTG2 001 SCLK1 010 AD8 011 LCD36 100–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 170 Table 6-71. PTGPF1 Field Descriptions Description Table 6-72. PTGPF2 Field Descriptions Description Freescale Semiconductor ...
Page 171
... LCD39 101–111Reserved 2–0 Port G4 Pin Mux Controls. G4 000 PTG4 001 CMPOUT1 010 RxD3 011 AD10 100 LCD38 101–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Parallel Input/Output ControlChapter 6 Parallel Input/Output Control Table 6-73. PTGPF3 Field Descriptions Description ...
Page 172
... CMPP4 010 AD13 011 PCNT1 100 LCD41 101–111Reserved 2–0 Port G6 Pin Mux Controls. G6 000 PTG6 001 CMPP3 010 AD12 011 PCNT0 100 LCD40 101–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 172 Table 6-74. PTGPF4 Field Descriptions Description Freescale Semiconductor ...
Page 173
... LCD43 100–111Reserved 2–0 Port H0 Pin Mux Controls. H0 000 PTH0 001 CMPP5 010 AD14 011 PCNT2 100 LCD42 101–111Reserved MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Parallel Input/Output ControlChapter 6 Parallel Input/Output Control Table 6-75. PTHPF1 Field Descriptions Description ...
Page 174
... Parallel Input/Output ControlChapter 6 Parallel Input/Output Control MC9S08GW64 MCU Series Reference Manual, Rev.3 174 Freescale Semiconductor ...
Page 175
... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several ...
Page 176
... X. MC9S08GW64 MCU Series Reference Manual, Rev.3 176 7 0 ACCUMULATOR A 16-BIT INDEX REGISTER H:X INDEX REGISTER (LOW STACK POINTER PROGRAM COUNTER CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-1. CPU Registers Freescale Semiconductor ...
Page 177
... For a more detailed explanation of how each instruction sets the CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Central Processor Unit (S08CPUV5)Chapter 7 Central Processor Unit (S08CPUV6) 177 ...
Page 178
... No carry out of bit 7 1 Carry out of bit 7 MC9S08GW64 MCU Series Reference Manual, Rev.3 178 CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 7-2. Condition Code Register Table 7-1. CCR Register Field Descriptions Description Freescale Semiconductor ...
Page 179
... In immediate addressing mode, the operand needed to complete the instruction is included in the object code immediately following the instruction opcode in memory. In the case of a 16-bit immediate operand, MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Central Processor Unit (S08CPUV5)Chapter 7 Central Processor Unit (S08CPUV6) NOTE ...
Page 180
... The index register pair is then incremented (H:X = H:X + 0x0001) after the operand has been fetched. This addressing mode is used only for the CBEQ instruction. MC9S08GW64 MCU Series Reference Manual, Rev.3 180 Freescale Semiconductor ...
Page 181
... The CPU sequence for an interrupt is: 1. Store the contents of PCL, PCH and CCR on the stack, in that order. 2. Set the I bit in the CCR. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Central Processor Unit (S08CPUV5)Chapter 7 Central Processor Unit (S08CPUV6) Resets, Interrupts, and System Configuration 181 ...
Page 182
... MCU was reset into active background mode), the oscillator is forced to remain active when the MCU enters stop mode. In this case serial BACKGROUND command is issued to the MCU through the background debug interface MC9S08GW64 MCU Series Reference Manual, Rev.3 182 Freescale Semiconductor ...
Page 183
... PPAGE value and the return address, the queue is refilled, and execution resumes with the next instruction after the corresponding CALL. MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Central Processor Unit (S08CPUV5)Chapter 7 Central Processor Unit (S08CPUV6) chapter for more details. 183 ...
Page 184
... However subroutine can be called from other pages, it must be terminated with an RTC. In this case, since RTC unstacks the PPAGE value as well as the return address, all accesses to the subroutine, even those made from the same page, must use CALL instructions. MC9S08GW64 MCU Series Reference Manual, Rev.3 184 Freescale Semiconductor ...
Page 185
... ASL oprx8,X b7 ASL ,X ASL oprx8,SP (Same as LSL) ASR opr8a Arithmetic Shift Right ASRA ASRX ASR oprx8,X ASR , ASR oprx8,SP Freescale Semiconductor Central Processor Unit (S08CPUV5)Chapter 7 Central Processor Unit (S08CPUV6) Object Code IMM DIR EXT IX2 IX1 IX SP2 9E D9 SP1 9E E9 IMM ...
Page 186
... Freescale Semiconductor Affect on CCR – – – – – – – – – – – – – – – – – – – – – – – – – – – – ...
Page 187
... CLR opr8a Clear A $00 CLRA X $00 CLRX H $00 CLRH M $00 CLR oprx8,X M $00 CLR ,X M $00 CLR oprx8,SP Freescale Semiconductor Central Processor Unit (S08CPUV5)Chapter 7 Central Processor Unit (S08CPUV6) Object Code REL REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL ...
Page 188
... F8 rfp pprpp 4 ff prpp Freescale Semiconductor Affect on CCR – – 1 – – – ...
Page 189
... LSL oprx8,X b7 LSL ,X (Same as ASL) LSL oprx8,SP LSR opr8a Logical Shift Right LSRA LSRX 0 LSR oprx8,X LSR ,X b7 LSR oprx8,SP Freescale Semiconductor Central Processor Unit (S08CPUV5)Chapter 7 Central Processor Unit (S08CPUV6) Object Code DIR INH INH IX1 IX SP1 9E 6C DIR EXT IX2 IX1 ...
Page 190
... Freescale Semiconductor Affect on CCR – – – – – 0 – – – – – – – – – – – ...
Page 191
... STX opr8a STX opr16a STX oprx16,X Store X (Low 8 Bits of Index Register) STX oprx8,X in Memory M (X) STX ,X STX oprx16,SP STX oprx8,SP Freescale Semiconductor Central Processor Unit (S08CPUV5)Chapter 7 Central Processor Unit (S08CPUV6) Object Code INH INH INH INH IMM DIR EXT IX2 ...
Page 192
... Freescale Semiconductor Affect on CCR – 1 – – – – – – – – – – – – – ...
Page 193
... V Overflow bit H Half-carry bit I Interrupt mask N Negative bit Z Zero bit C Carry/borrow bit Freescale Semiconductor Central Processor Unit (S08CPUV5)Chapter 7 Central Processor Unit (S08CPUV6) Object Code INH INH Addressing Modes: DIR Direct addressing mode EXT Extended addressing mode IMM Immediate addressing mode INH ...
Page 194
... IMM 2 DIR 3 EXT 3 IX2 TXA AIX STX STX STX INH 2 IMM 2 DIR 3 EXT 3 IX2 Opcode HCS08 Cycles Hexadecimal SUB Instruction Mnemonic Addressing Mode Number of Bytes 1 IX Freescale Semiconductor SUB SUB 2 IX1 CMP CMP 2 IX1 SBC SBC 2 IX1 CPX CPX 2 IX1 1 IX ...
Page 195
... IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E) MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Central Processor Unit (S08CPUV5)Chapter 7 Central Processor Unit (S08CPUV6) Table 7-3. Opcode Map (Sheet Read-Modify-Write Control 9E60 6 ...
Page 196
... Central Processor Unit (S08CPUV5)Chapter 7 Central Processor Unit (S08CPUV6) MC9S08GW64 MCU Series Reference Manual, Rev.3 196 Freescale Semiconductor ...
Page 197
... The bus clock to the KBI module can be gated on and off using the KBI bit in SCGC1. This bit is cleared after any reset, which disables the bus clock to this module. To conserve power, the KBI bit can be cleared to disable the clock to this module. See MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Section 5.7, “Peripheral Clock Gating,” for details. 197 ...
Page 198
... PTC3/SS1/LCD5 PTC4/FTMCH0/RxD1/LCD6 PTC5/FTMCH1/TxD1/LCD7 PTC6/PCNTCH0/RxD3/LCD8 PTC7/PCNTCH1/TxD3/LCD9 PTD0/KBIP0/MOSI2/LCD10 PTD1/KBIP1/MISO2/LCD11 PTD2/KBIP2/SCLK2/LCD12 PTD3/KBIP3/SS2/LCD13 PTD4/KBIP4/LCD14 PTD5/KBIP5/CLKOUT/LCD15 PTD6/KBIP6/LCD16 PTD7/KBIP7/LCD17 PTE0/LCD18 PTE1/LCD19 PTE2/LCD20 PTE3/LCD21 PTE4/LCD22 PTE5/LCD23 PTE6/LCD24 PTE7/LCD25 PTF0/LCD26 PTF1/LCD27 PTF2/LCD28 PTF3/LCD29 PTF4/LCD30 PTF5/LCD31 PTF6/MTIMCLK/AD4/LCD32 PTF7/FTMCLK/AD5/LCD33 PTG0/MOSI1/AD6/LCD34 PTG1/MISO1/AD7/LCD35 PTG2/SCLK1/AD8/LCD36 PTG3/SS1/AD9/LCD37 PTG4/CMPOUT1/RxD3/AD10/LCD38 PTG5/CMPOUT2/TxD3/AD11/LCD39 PTG6/CMPP3/AD12/PCNT0/LCD40 PTG7/CMPP4/AD13/PCNT1/LCD41 PTH0/CMPP5/AD14/PCNT2/LCD42 PTH1/RTCCLKOUT/CMPP6/AD15/LCD43 Freescale Semiconductor ...
Page 199
... When the microcontroller is in active background mode, the KBI will continue to operate normally. 8.1.4 Block Diagram The block diagram for the keyboard interrupt module is shown MC9S08GW64 MCU Series Reference Manual, Rev.3 Freescale Semiconductor Keyboard Interrupt (S08KBIV2) Modes of Operation Figure 8-2. 199 ...
Page 200
... KBACK V RESET DD CLR KEYBOARD INTERRUPT FF KBMOD Figure 8-2. KBI Block Diagram Table 8-1. Table 8-1. Signal Properties Function Keyboard interrupt pins Memory chapter for the absolute address assignments for BUSCLK KBF SYNCHRONIZER STOP BYPASS STOP KBI INTERRU PT KBIE I/O I Freescale Semiconductor ...