PIC32MX320F064HT-40V/PT Microchip Technology, PIC32MX320F064HT-40V/PT Datasheet - Page 64

• Manufacturer Part Number: PIC32MX320F064HT-40V/PT
• Description: 64 KB Flash, 16 KB RAM, 40 MHz, 10-Bit ADC, DMA 64 TQFP 10x10x1mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX320F064HT-40V/PT

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 4-14:
TABLE 4-15:
Legend:
Note
Legend:
Note
3000 DMACON
3010
3020 DMAADDR
3030 DCRCCON
3040 DCRCDATA
3050 DCRCXOR
1:
1:
DMASTAT
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
(1)
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
DMA GLOBAL REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY
DMA CRC REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY
31/15
31/15
ON
—
—
—
—
—
—
—
30/14
30/14
—
—
—
—
—
—
—
—
29/13
29/13
SIDL
—
—
—
—
—
—
—
SUSPEND
28/12
28/12
—
—
—
—
—
—
—
27/11
27/11
—
—
—
—
—
—
—
26/10
26/10
—
—
—
—
—
—
—
PLEN<3:0>
25/9
25/9
—
—
—
—
—
—
—
DCRCDATA<15:0>
DMAADDR<31:0>
DCRCXOR<15:0>
24/8
24/8
—
—
—
—
—
—
—
Bits
Bits
CRCEN
23/7
23/7
—
—
—
—
—
—
—
CRCAPP
22/6
22/6
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
21/5
21/5
—
—
—
—
—
—
—
—
20/4
20/4
Section 12.1.1 “CLR, SET and INV Registers”
—
—
—
—
—
—
—
—
RDWR
19/3
19/3
—
—
—
—
—
—
—
18/2
18/2
—
—
—
—
—
—
—
—
(1)
for more information.
17/1
17/1
—
—
—
DMACH<1:0>
—
—
—
CRCCH<1:0>
16/0
16/0
for more
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000