PIC32MX440F128LT-80V/BG Microchip Technology, PIC32MX440F128LT-80V/BG Datasheet - Page 84

• Manufacturer Part Number: PIC32MX440F128LT-80V/BG
• Description: 128 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x10x1.20mm
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX440F128LT-80V/BG

• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 32 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: XBGA-121
• Operating Temperature Range: - 40 C to + 105 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: -
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

TABLE 4-43:
Legend:
Note
53A0
53B0
53C0
53D0
53E0
53F0
5380
5390
1:
2:
3:
4:
U1EP10
U1EP12
U1EP13
U1EP14
U1EP15
U1EP11
U1EP8
U1EP9
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
Registers”
This register does not have associated CLR, SET, and INV registers.
All bits in this register are read-only; therefore, CLR, SET, and INV registers are not supported.
The reset value for this bit is undefined.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
USB REGISTERS MAP
for more information.
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
28/12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(CONTINUED)
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
24/8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits
23/7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
EPCONDIS
20/4
—
—
—
—
—
—
—
—
EPRXEN
EPRXEN
EPRXEN
EPRXEN
EPRXEN
EPRXEN
EPRXEN
EPRXEN
19/3
—
—
—
—
—
—
—
—
EPTXEN
EPTXEN
EPTXEN
EPTXEN
EPTXEN
EPTXEN
EPTXEN
EPTXEN
Section 12.1.1 “CLR, SET and INV
18/2
—
—
—
—
—
—
—
—
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
EPSTALL
17/1
—
—
—
—
—
—
—
—
EPHSHK 0000
EPHSHK 0000
EPHSHK 0000
EPHSHK 0000
EPHSHK 0000
EPHSHK 0000
EPHSHK 0000
EPHSHK 0000
16/0
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000