PIC32MX460F512LT-80V/BG Microchip Technology, PIC32MX460F512LT-80V/BG Datasheet - Page 28

• Manufacturer Part Number: PIC32MX460F512LT-80V/BG
• Description: 512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x10x1.20mm
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512LT-80V/BG

• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: XBGA-121
• Operating Temperature Range: - 40 C to + 105 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: -
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PIC32MX3XX/4XX
TABLE 1-1:
DS61143H-page 28
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
PMD9
PMD10
PMD11
PMD12
PMD13
PMD14
PMD15
PMRD
PMWR
PMALL
PMALH
V
V
V
D+
D-
USBID
ENVREG
TRCLK
TRD0
TRD1
TRD2
TRD3
PGED1
PGEC1
Legend: CMOS = CMOS compatible input or output
Note 1:
Pin Name
USB
BUS
BUSON
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Pin numbers are provided for reference only. See the
QFN/TQFP
64-pin
60
61
62
63
64
53
52
30
29
34
35
11
37
36
33
57
16
15
—
—
—
—
—
—
—
—
—
—
—
—
—
1
2
3
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number
100-pin
TQFP
100
93
94
98
99
90
89
88
87
79
80
83
84
82
81
44
43
54
55
20
57
56
51
86
91
97
96
95
92
25
24
3
4
5
(1)
121-pin
XBGA
H10
K10
J11
A4
B4
B3
A2
A1
D3
C1
D2
A5
E6
B6
D8
D7
C7
B8
C8
K7
H8
H9
H1
A7
C5
A3
C3
C4
B5
K2
K1
A6
A9
L8
Type
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
P
I
I
I
I
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
TTL/ST
Analog
Analog
Analog
Buffer
Type
ST
ST
ST
ST
—
—
—
—
—
—
—
—
—
—
—
Analog = Analog input
O = Output
“Pin
Parallel Master Port Data (De-multiplexed Master
mode) or Address/Data (Multiplexed Master modes).
Parallel Master Port Read Strobe.
Parallel Master Port Write Strobe.
Parallel Master Port Address Latch Enable low-byte
(Multiplexed Master modes).
Parallel Master Port Address Latch Enable high-byte
(Multiplexed Master modes).
USB Bus Power Monitor.
USB Internal Transceiver Supply. If the USB module
is not used, this pin must be connected to V
USB Host and OTG Bus Power Control Output.
USB D+.
USB D-.
USB OTG ID Detect.
Enable for On-Chip Voltage Regulator.
Trace Clock.
Trace Data Bits 0-3.
Data I/O pin for programming/debugging
communication channel 1.
Clock input pin for programming/debugging
communication channel 1.
Diagrams” section for device pin availability.
Description
© 2011 Microchip Technology Inc.
P = Power
I = Input
DD
.