PIC32MX695F512L-80V/PT Microchip Technology, PIC32MX695F512L-80V/PT Datasheet - Page 81
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PIC32MX695F512L-80V/PT
Manufacturer Part Number
PIC32MX695F512L-80V/PT
Description
512 KB Flash, 128 KB RAM, USB-OTG, Ethernet, 80 MHz, 10-Bit ADC, DMA 100 TQFP 12
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.PIC32MX575F256H-80VPT.pdf
(256 pages)
Specifications of PIC32MX695F512L-80V/PT
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX695F512L-80V/PT
Manufacturer:
MICROCHIP
Quantity:
1 000
Company:
Part Number:
PIC32MX695F512L-80V/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC32MX695F512L-80V/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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TABLE 4-13:
Legend:
Note
6000 U1MODE
6010
6020
6030
6040
6200 U4MODE
6210
6220
6230
6240
6400 U3MODE
6410
6420
6430
6440
6600 U6MODE
6610
6620
1:
U1RXREG
U4RXREG
U3RXREG
U1TXREG
U4TXREG
U3TXREG
U6TXREG
U1BRG
U4BRG
U3BRG
U1STA
U4STA
U3STA
U6STA
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
UART1 THROUGH UART6 REGISTER MAP
31/15
ON
ON
ON
ON
UTXISEL<1:0>
UTXISEL<1:0>
UTXISEL<1:0>
UTXISEL<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
FRZ
FRZ
FRZ
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXINV
UTXINV
UTXINV
UTXINV
29/13
SIDL
SIDL
SIDL
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
URXEN
URXEN
URXEN
URXEN
28/12
IREN
IREN
IREN
IREN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXBRK
UTXBRK
UTXBRK
UTXBRK
RTSMD
RTSMD
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXEN
UTXEN
UTXEN
UTXEN
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXBF
UTXBF
UTXBF
UTXBF
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UEN<1:0>
UEN<1:0>
ADM_EN
ADM_EN
ADM_EN
ADM_EN
TRMT
TRMT
TRMT
TRMT
24/8
TX8
RX8
TX8
RX8
TX8
RX8
TX8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG<15:0>
BRG<15:0>
BRG<15:0>
Bits
WAKE
WAKE
WAKE
WAKE
23/7
URXISEL<1:0>
URXISEL<1:0>
URXISEL<1:0>
URXISEL<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LPBACK
LPBACK
LPBACK
LPBACK
22/6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
ABAUD
ADDEN
ABAUD
ADDEN
ABAUD
ADDEN
ABAUD
ADDEN
21/5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXINV
RIDLE
RXINV
RIDLE
RXINV
RIDLE
RXINV
RIDLE
Transmit Register
Transmit Register
Transmit Register
Transmit Register
Receive Register
Receive Register
Receive Register
20/4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADDR<7:0>
ADDR<7:0>
ADDR<7:0>
ADDR<7:0>
BRGH
BRGH
BRGH
BRGH
PERR
PERR
PERR
PERR
19/3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
FERR
FERR
FERR
FERR
18/2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PDSEL<1:0>
PDSEL<1:0>
PDSEL<1:0>
PDSEL<1:0>
for more information.
OERR
OERR
OERR
OERR
17/1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
URXDA
URXDA
URXDA
URXDA
STSEL
STSEL
STSEL
STSEL
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
0000
0110
0000
0000
0000
0000
0000
0000
0000
0000
0000
0110
0000
0000
0000
0000
0000
0000
0000
0000
0000
0110
0000
0000
0000
0000
0000
0000
0000
0000
0000
0110
0000
0000
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