SDXILEVK/NOPB National Semiconductor, SDXILEVK/NOPB Datasheet - Page 22
SDXILEVK/NOPB
Manufacturer Part Number
SDXILEVK/NOPB
Description
SDI EVAL BOARD FOR XILINX
Manufacturer
National Semiconductor
Series
-r
Specifications of SDXILEVK/NOPB
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
www.national.com
ADD
'h
30
Name
CLK_Delay
Bits
The three msbs from this register are used to insert a programmable delay into the TXCLK path,
if the host FPGA does not provide adequate setup and hold times for the SER, this register can
be used to shift the window in 125ps increments.
7:5
4:0
Field
TCLK Delay
Reserved
22
R/W
r/w
Default
011'b
Description
000'b is minimum delay setting, 111'b is
maximum delay setting, each step is
approx 125ps