MK20DN512ZVLL10 Freescale Semiconductor, MK20DN512ZVLL10 Datasheet - Page 58

KINETIS 512K USB

MK20DN512ZVLL10

Manufacturer Part Number
MK20DN512ZVLL10
Description
KINETIS 512K USB
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MK20DN512ZVLL10

Processor Series
K20
Core
ARM Cortex M4
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
128 KB
Interface Type
USB, CAN, SPI, I2C, UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
2
Number Of Timers
2
Operating Supply Voltage
1.71 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
LQFP-100
Operating Temperature Range
- 40 C to + 105 C
Processor To Be Evaluated
MK20DN512ZVLL10
Supply Current (max)
185 mA
Lead Free Status / Rohs Status
 Details

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Part Number:
MK20DN512ZVLL10
Manufacturer:
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Quantity:
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Peripheral operating requirements and behaviors
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I
6.8.4 CAN switching specifications
See
6.8.5 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
58
Symbol
C
ESR
I
Num
DS1
DS2
DS3
DS4
DS5
DS6
DS7
DS8
LIM
OUT
General switching
External output capacitor
External output capacitor equivalent series
resistance
Short circuit current
Description
Operating voltage
Frequency of operation
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
DSPI_SCK to DSPI_PCSn invalid delay
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
Table 40. Master mode DSPI timing (limited voltage range)
Table 39. USB VREG electrical specifications
K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
specifications.
Description
(continued)
1.76
Min.
1
(t
(t
(t
SCK
BUS
BUS
2 x t
Min.
2.7
−2
15
/2) − 2
2
2
0
x 2) −
x 2) −
BUS
Typ.
290
2.2
1
(t
SCK
Max.
3.6
8.5
25
/2) + 2
Max.
8.16
100
Freescale Semiconductor, Inc.
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
Unit
mA
μF
Notes
Load
Notes
1
2
.
Datasheet pdf - http://www.DataSheet4U.net/

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