MK20DX128ZVLQ10 Freescale Semiconductor, MK20DX128ZVLQ10 Datasheet - Page 35

• Manufacturer Part Number: MK20DX128ZVLQ10
• Description: KINETIS 128KFLEX USB
• Manufacturer: Freescale Semiconductor

Specifications of MK20DX128ZVLQ10

• Processor Series: K20
• Core: ARM Cortex M4
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 128 KB
• Interface Type: USB, CAN, SPI, I2C, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 2
• Number Of Timers: 2
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-144
• Operating Temperature Range: - 40 C to + 105 C
• Processor To Be Evaluated: MK20DX128ZVLQ10
• Supply Current (max): 185 mA
• Lead Free Status / Rohs Status: No

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6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
The following timing numbers indicate when data is latched or driven onto the external
bus, relative to the Flexbus output clock (FB_CLK). All other timing relationships can be
derived from these values.
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
Freescale Semiconductor, Inc.
and FB_TS.
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
Num
FB1
FB2
FB3
FB4
FB5
Operating voltage
Frequency of operation
Clock period
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
Description
Table 25. Flexbus limited voltage range switching specifications
K20 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
EP3
EP5
Figure 9. EzPort Timing Diagram
EP6
EP7
EP4
EP8
EP9
Peripheral operating requirements and behaviors
Min.
EP2
2.7
0.5
8.5
0.5
20
—
—
FB_CLK
Max.
11.5
3.6
—
—
—
—
MHz
Unit
ns
ns
ns
ns
ns
V
Notes
1
1
2
2
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