MK60DN512ZVLQ10 Freescale Semiconductor, MK60DN512ZVLQ10 Datasheet - Page 57

• Manufacturer Part Number: MK60DN512ZVLQ10
• Description: KINETIS 512K ENET
• Manufacturer: Freescale Semiconductor

Specifications of MK60DN512ZVLQ10

• Processor Series: K60
• Core: ARM Cortex M4
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• Interface Type: USB, CAN, SPI, I2C, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 2
• Number Of Timers: 2
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-144
• Operating Temperature Range: - 40 C to + 105 C
• Processor To Be Evaluated: MK60DN512ZVLQ10
• Supply Current (max): 185 mA
• Lead Free Status / Rohs Status: No

6.8.1 Ethernet switching specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
6.8.1.1 MII signal switching specifications
The following timing specs meet the requirements for MII style interfaces for a range of
transceiver devices.
Freescale Semiconductor, Inc.
Symbol
MII1
MII2
MII3
MII4
MII5
MII6
MII7
MII8
—
—
RXCLK frequency
RXCLK pulse width high
RXCLK pulse width low
RXD[3:0], RXDV, RXER to RXCLK setup
RXCLK to RXD[3:0], RXDV, RXER hold
TXCLK frequency
TXCLK pulse width high
TXCLK pulse width low
TXCLK to TXD[3:0], TXEN, TXER invalid
TXCLK to TXD[3:0], TXEN, TXER valid
Description
TXCLK (input)
TXD[n:0]
TXEN
TXER
K60 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
Figure 20. MII transmit signal timing diagram
Table 38. MII signal switching specifications
MII8
MII6
Valid data
Valid data
Valid data
MII5
MII7
Peripheral operating requirements and behaviors
35%
35%
35%
35%
Min.
—
—
—
5
5
2
Max.
65%
65%
65%
65%
25
25
25
—
—
—
RXCLK
RXCLK
TXCLK
TXCLK
period
period
period
period
MHz
MHz
Unit
ns
ns
ns
ns
57