LC4256ZE-B-EVN Lattice, LC4256ZE-B-EVN Datasheet - Page 7

• Manufacturer Part Number: LC4256ZE-B-EVN
• Description: Programmable Logic Development Tools ispMACH 4256ZE Breakout Board
• Manufacturer: Lattice
• Series: ispMACH®r
• Type: CPLDr

Specifications of LC4256ZE-B-EVN

• Contents: Board, Cable
• Lead Free Status / Rohs Status: Details
• For Use With/related Products: LC4256ZE-5TN144C

Lattice Semiconductor
USB port or optionally with external power. You may create or modify CPLD program files using ispLEVER Classic
software and reprogram the board using ispVM software.
Figure 3. ispMACH 4000ZE Breakout Board Block Diagram
Table 1 describes the components on the board and the interfaces it supports.
Table 1. Breakout Board Components and Interfaces
Subsystems
This section describes the principle subsystems for the ispMACH 4256ZE Breakout Board in alphabetical order.
Clock Sources
All clocks for the counter demonstration designs originate from the ispMACH 4256ZE CPLD on-chip oscillator and
timer (OSCTIMER) block. You may use an expansion header landing to drive a CPLD input with an external clock
source.
Expansion Header Landings
The expansion header landings provide access to user GPIOs, primary inputs, clocks, and Bank 0/1 VCCO pins of
the ispMACH 4256ZE. The remaining pins serve as power supplies for external connections. Each landing is con-
figured as one 2x20 100 mil.
Table 2. Expansion Connector Reference
Circuits
USB Controller
USB Mini-B
Components
LC4256ZE
Interfaces
LED Array
Four 2x20 header landings
1x8 header landing
4x15 prototype area
Component/Interface
Socket
USB Cable
A/Mini-B
USB Mini B
Socket
Circuit
I/O
CPLD
Output
I/O
I/O
Reference Designators
Part Number
2x20 Header
2x20 Header
Landing (J3)
Landing (J4)
Controller
Type
USB
Item
U2: FT2232H
J1:USB_MINI_B
U4: LC4256ZE-5TN144C
D8-D1
J3: header_2x20
J4: header_2x20
J5: header_2x20
J6: header_2x20
J1: header_1x8
J9
Programming
Schematic Reference
JTAG
20 GPIO
35 GPIO
J3, J4, J5, J6
header_2x20
ispMACH4256ZE-5T
7
N144C
Description
USB-to-JTAG interface and dual USB UART/FIFO IC
Programming and debug interface
256-macrocell CPLD packaged in a 20 x 20mm,
144-pin TQFP
Red LEDs
User-definable I/O
Optional JTAG interface
Prototype area 100mil centered holes
ispMACH 4256ZE Breakout Board
40 GPIO
15 GPIO
8
8
Evaluation Kit User’s Guide
Description
2x20 Header
2x20 Header
Landing (J5)
Landing (J6)
1x8 JTAG Header
Array
Landing (J1)
LED