MCIMX537CVV8C Freescale Semiconductor, MCIMX537CVV8C Datasheet
MCIMX537CVV8C
Specifications of MCIMX537CVV8C
Available stocks
Related parts for MCIMX537CVV8C
MCIMX537CVV8C Summary of contents
Page 1
... The flexibility of the i.MX53xD architecture allows for its use in a wide variety of applications. As the heart of This document contains information on a new product. Specifications and information herein are subject to change without notice. © 2011 Freescale Semiconductor, Inc. All rights reserved. Document Number: IMX53CEC Rev. 1, 3/2011 MCIMX53xD ...
Page 2
... Freescale representative. The i.MX53xD application processor is a follow-on to the i.MX51, with improved performance, power efficiency, and multimedia capabilities. i.MX53xD Applications Processors for Consumer Products, Rev ® ES 2.0 3D graphics accelerator (33 Mtri/s, 200 Mpix/s, and 2 S serial audio, among others). Freescale Semiconductor ...
Page 3
... DDR2-800, LV-DDR2-800 or DDR3-800 Gbyte — 32bit LPDDR2 — 8/16-bit NAND SLC/MLC Flash MHz, 4/8/14/16-bit ECC — 8,16-bit NOR Flash, PSRAM & cellular RAM. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 1. Ordering Information Case Features Temperature Range ( ...
Page 4
... LVDS serial ports: one dual channel port up to 165 Mpix/s or two independent single channel ports MP/s (for example, WXGA @ 60 Hz) each. — TV-out/VGA port up to 150 Mpix/s (for example, 1080p60). • Camera sensors: i.MX53xD Applications Processors for Consumer Products, Rev NOTE Freescale Semiconductor ...
Page 5
... On-chip oscillator amplifier supporting 32.768 kHz external crystal • On-chip LDO voltage regulators for PLLs Security functions are enabled and accelerated by the following hardware: • ARM TrustZone including the TZ architecture (separation of interrupts, memory mapping, and so on) i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Introduction 5 ...
Page 6
... Functions such as video hardware acceleration, 2D and 3D hardware graphics acceleration, and Macrovision enabled for specific part numbers. 2 Architectural Overview The following subsections provide an architectural overview of the i.MX53xD processor system. i.MX53xD Applications Processors for Consumer Products, Rev NOTE TM video copy protection may not be Table 1. Freescale Semiconductor ...
Page 7
... Audio, Power Mngmnt. Ethernet 10/100 Mbps IrDA XVR The numbers in brackets indicate number of module instances. For example, PWM (2) indicates two separate PWM peripherals. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor NOR/NAND Battery Ctrl Camera LVDS Camera Flash Device (2) (WSXGA+) (2) ...
Page 8
... The security control registers (SCR) of the CSU are set during boot time by the high assurance boot (HAB) code and are locked to prevent further writing. Table 2 describes these Freescale Semiconductor ...
Page 9
... Connectivity Audio Interface Peripherals i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Brief Description The debug system provides real-time trace debug capability of both instructions and data. It supports a trace protocol that is an integral part of the ARM Real Time Debug solution (RealView). ...
Page 10
... EXTMC environment of a vehicle, cost-effectiveness and required bandwidth. The FLEXCAN is a full implementation of the CAN protocol specification, Version 2.0 B (ISO 11898), which supports both standard and extended message frames at 1 Mbps. Freescale Semiconductor ...
Page 11
... IC Identification Security Module i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Brief Description These modules are used for general purpose input/output to external ICs. Each GPIO module supports bits of I/O. Each GPT is a 32-bit “free-running” or “set and forget” mode timer with a programmable prescaler and compare and capture register ...
Page 12
... The on-chip memory controller (OCRAM) module interface between the system’s AXI bus, to the internal (on-chip) SRAM memory module used for controlling the 128 KB multimedia RAM, through a 64-bit AXI bus. Supports secure and regular boot modes. The ROM controller supports ROM patching. Freescale Semiconductor ...
Page 13
... Memory Access Control Peripherals i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Brief Description Protecting read only data from modification is one of the basic elements in trusted platforms. The run-time integrity checker, version 3 (RTIC) block is a data-monitoring device responsible for ensuring that the memory content is not corrupted during program execution ...
Page 14
... Each SSI has two pairs FIFOs and hardware support for an external DMA controller in order to minimize its impact on system performance. The second pair of FIFOs provides hardware interleaving of a second audio stream, which reduces CPU overhead in use cases where two time slots are being used simultaneously. Freescale Semiconductor ...
Page 15
... USB USB Controller Connectivity Peripherals i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Brief Description The IEEE 1588-2002 (version 1) standard defines a precision time protocol (PTP) - which is a time-transfer protocol that enables synchronization of networks (for example, Ethernet high degree of accuracy and precision ...
Page 16
... still not served, the TZ WDOG asserts a security violation signal to the CSU. The TZ WDOG module cannot be programmed or deactivated by a normal mode SW. Provides a crystal oscillator amplifier that supports a 24-MHz external crystal Provides a crystal oscillator amplifier that supports a 32.768-kHz external crystal Freescale Semiconductor ...
Page 17
... These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Section 6, “Package Information and Contact NOTE Table 3. i.MX53xD Chip-Level Conditions CAUTION ...
Page 18
... Unit –0.3 1.35 V –0.3 1.35 V –0.5 3.6 V –0.5 3.3 V — 5. –0.3 3. –0.5 OVDD +0 — 2000 — 500 o –40 150 C Symbol Value Unit R 28 °C/W θ °C/W θ °C/W θJMA R 13 °C/W θJMA R 6 °C/W θ °C/W θJC Ψ 4 °C/W JT Freescale Semiconductor ...
Page 19
... LVDS interface Supply NVCC_LVDS_BG LVDS Band Gap Supply DDR Supply DDR2 range DDR Supply LPDDR2 range NVCC_EMI_DRAM DDR Supply LV-DDR2 range DDR Supply DDR3 range i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 6. i.MX53xD Operating Ranges Parameter Electrical Characteristics Minimum Nominal Maximum 0 ...
Page 20
... Nominal Maximum Unit — 3.3 V 1.8 1.95 2.775 3.1 V 3.3 3.6 2.75 2.91 V 1.8 or 3.1 V 2.775 1.3 1.35 V 1.8 or 3.1 V 2.775 2.5 2.75 V 3.3 3.6 V — — — — 2.5 2.63 V 1.3 1.35 V 2.5 2. 105 C Freescale Semiconductor ...
Page 21
... CKIL Oscillator CKIH1, CKIH2 Operating Frequency XTAL Oscillator 1 External oscillator or a crystal with internal oscillator amplifier. 2 Recommended nominal frequency 32.768 kHz. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 7. External Input Clock Frequency Symbol Min f — 32.768 ckil f , See Table 31, " ...
Page 22
... Use maximal IO Eq Use maximal IO Eq Use maximal IO Eq Use maximal IO Eq Use maximal IO Eq Use maximal IO Eq Use maximal IO Eq Max Current Unit 1700 mA 800 mA 100 325 800 mA 650 mA 250 mA 200 mA & N=13 Freescale Semiconductor ...
Page 23
... USB interface current consumption. Table 9. USB Interface Current Consumption Parameter Analog Supply 3.3 V USB_H1_VDDA33 USB_OTG_VDDA33 i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Conditions Max Current Use maximal IO Eq Use maximal IO Eq Use maximal IO Eq Use maximal IO Eq ...
Page 24
... VDD_REG used as their i.MX53xD Applications Processors for Consumer Products, Rev Conditions Typical @ 25 °C RX 6.5 Full Speed TX 6 High Speed Full Speed High Speed TX 8 Suspend Max Unit — — mA — — μA Freescale Semiconductor ...
Page 25
... This is due to ESD diode protection circuit, that may cause current leakage if one of the supplies is powered ON before the other. The POR_B input must be immediately asserted at power-up and remain asserted until after the last power rail reaches its working voltage. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor NOTE Electrical Characteristics 25 ...
Page 26
... If fuse writing is required, VDD_FUSE should be powered ON after NVCC_CKIH is stable. i.MX53xD Applications Processors for Consumer Products, Rev 90% 90% Δt > 0 90% Δt > 0 Δt > 0 Δt > 0 90% Δt > 0 90% Figure 2. Power Up Detailed Sequence NOTE 90% 90% Δt > 0 Δt > 0 90% Δt > 0 90% Δt > Freescale Semiconductor ...
Page 27
... Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes • Low Voltage I/O (LVIO) • Ultra High Voltage I/O (UHVIO) • LVDS I/O i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 6 Ultra High voltage I/O (UHVIO) supplies , Electrical Characteristics . A deviation of few ) 27 ...
Page 28
... Table 6, unless otherwise noted. Min Typ Max OVDD – 0.15 — — 0.8*OVDD — — 0.15 × 0.2 OVDD –0.85 –1.7 — — –2.5 –3.4 0.9 1.9 — — 2.9 3.8 –2.1 –4.2 — — –6.3 –8.4 Freescale Semiconductor Unit ...
Page 29
... DDR2 Mode I/O DC Parameters The DDR2 interface fully complies with JESD79-2E DDR2 JEDEC standard release April, 2008. The parameters in Table 11 are guaranteed per the operating ranges in i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Symbol Test Conditions × Iol Vout = 0.2 ...
Page 30
... OVDD+0.3 –0.3 — Vref-0.125V –0.3 — OVDD+0.3 0.25 — OVDD+0.6 Vref Vref + 0.04 — 0.07 5 — 2 360 8 — 125 — 1 Min Typ Max — — — — 0.1*OVDD 0.5*OVDD 0.51*OVDD — OVDD Freescale Semiconductor Unit kΩ Unit ...
Page 31
... Over/undershoot peak Over/undershoot area (above OVDD or below OVSS) Termination Voltage Input current (no pull-up/down) Pull-up/Pull-down impedance mismatch 240 Ω unit calibration resolution Keeper Circuit Resistance i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Vil(dc) — Vih(diff) Vil(diff) Iin VI=OVDD — — ...
Page 32
... OVDD — — 0.5 × OVDD — — — 1.7 250 120 — — 161 0.12 — — 76 0.12 — — 36 0.12 — — 0. — 125 — — 125 — Freescale Semiconductor Unit μA μA μA μA kΩ ...
Page 33
... Input current (22 kΩ Pull-up) Input current (75 kΩ Pull-up) Input current (100 kΩ Pull-up) Input current (360 kΩ Pull-down) Keeper Circuit Resistance i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table Symbol Test Conditions Voh Iout = –1mA OVDD–0.15 Iout= specified Ioh 0 ...
Page 34
... Applications Processors for Consumer Products, Rev Symbol Test Conditions V Rload=100Ω OD padP, –padN 1.125 OS NOTE Min Typ Max 250 350 450 1.25 1.375 1.6 0.9 1.025 1.25 1.2 1.375 Figure 4). Freescale Semiconductor Unit mV V ...
Page 35
... OVDD Vref1 Vref 0 Vovdd – Vref1 Rpu = Rpd = Vovdd – Vref2 Figure 4. Impedance Matching Load for Measurement i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor OVDD PMOS (Rpu) Ztl Ω inches pad NMOS (Rpd) OVSS Vref2 × Ztl Vref1 Vref2 × ...
Page 36
... OVDD 2.775 V OVDD 1.875 V 104 150 134 Typ Max OVDD OVDD OVDD OVDD 1.875 V 3.3 V 1.65 V 3.6 V 114 124 135 198 118 126 154 179 Freescale Semiconductor Unit 250 125 Ω 243 122 Ω Unit 206 Ω 103 69 217 Ω 109 72 ...
Page 37
... Output Pad Slew Rate (High Drive) Output Pad Slew Rate (Medium Drive) 1 Output Pad Slew Rate (Low Drive) i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor From Output Test Point Under Test CL CL includes package, probe and fixture capacitance Figure 5. Load Circuit for Output ...
Page 38
... Freescale Semiconductor Unit mA/ns ns Unit V/ns V/ns V/ns V/ns mA/ns mA/ns mA/ns mA/ns ns ...
Page 39
... AC input logic low 2 AC differential input high voltage AC differential input low voltage Input AC differential cross point voltage Over/undershoot peak Over/undershoot area (above OVDD or below OVSS) i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Symbol Test Condition Vih(ac) — Vil(ac) — Vid(ac) — 3 ...
Page 40
... Min Typ Max — OVDD Vref 0.175 0 — – 0.35 — — 0.15 – — Vref + 0.15 0.15 – — Vref + 0.15 2.5 — 5 — — 0.2 0.1 Table 24 and Freescale Semiconductor Unit V/ns ns Unit V/ns ns ...
Page 41
... VIL to VIH for rising edge and between VIH to VIL for falling edge. 2 Hysteresis mode is recommended for inputs with transition times greater than 25 ns. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Symbol Test Condition trm — Test ...
Page 42
... Max — — 1.72/1.92 3.46/3.70 — — 2.38/2.56 5.07/5.25 — — 4.55/4.58 10.04/9.94 1.05/0.94 — — 0.52/0.49 0.76/0.71 — — 0.36/0.34 0.40/0.93 — — 0.18/0.18 — — 82.8 — — 65.6 — — 43.1 — — Freescale Semiconductor Unit ns V/ns mA/ns ns ...
Page 43
... Duration of RESET_IN to be qualified as valid (input slope = 5 ns) 4.6.2 WDOG Reset Timing Parameters Figure 9 shows the WDOG reset timing and WATCHDOG_RST (Input) i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Symbol Test Condition t SKD Rload = 100 Ω, t TLH Cload = 2 pF ...
Page 44
... Unit — 40.0 MHz — 0.3 — NVCC_CKIH — VDD Vp Min Typ Max 10 — 100 10 — 40 300 — 1025 1 — — 15 –67108862 — 67108862 1 — 67108863 48.5 50 51.5 Freescale Semiconductor Unit T CKIL V V Unit MHz MHz MHz — — — — % ...
Page 45
... Figure 33 demonstrates several examples of clock frequency settings. emi_slow_clk (MHz) nfc_podf (Division Factor) 100 (Boot mode) i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Test Conditions/Remarks — — — FPL mode, integer and fractional 300 MHz @ avdd = 1 ...
Page 46
... Setting the rhoh > also recommended that the rhoh (RE_B high to output high-Z). In most devices, the rhz NF1 NF3 NF5 NF8 NF9 command Figure 10. Command Latch Cycle Timing T-Clock Period (ns) 33. 44.33 22 NF2 NF4 Freescale Semiconductor ...
Page 47
... NFWE_B NFALE NFIO[7:0] NFCE_B NFWE_B NFIO[15:0] NFCE_B NFRE_B NFRB_B NFIO[15:0] Figure 13. Read Data Latch Timing, Asymmetric Mode i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor NF4 NF3 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address Figure 11. Address Latch Cycle Timing ...
Page 48
... NFCE_B NFRE_B NFRB_B NF12 NFIO[15:0] Figure 14. Read Data Latch Timing, Symmetric Mode NFCLE NFCE_B NFWE_B NFRE_B NFRB_B i.MX53xD Applications Processors for Consumer Products, Rev NF14 NF15 NF13 NF16 Data from NF NF19 NF20 NF21 NF22 Figure 15. Other Timing Parameters NF18 Freescale Semiconductor ...
Page 49
... MHz). 3 NF17 is defined only in asymmetric operation mode. NF17 max value is equivalent to max “emi_slow_clk” of the system. aclk i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 34. NFC—Timing Characteristics Symbol Asymmetric Mode Min 0.1 CLS t T – ...
Page 50
... Reference Manual External Signals and Pin Multiplexing Chapter, and IOMUXC Controller Chapter Nomenclature EIM_BCLK EIM_CSx EIM_RW EIM_OE EIM_EBx EIM_LBA EIM_A[25:16], EIM_DA[15:0] EIM_DAx (Addr/Data muxed mode) EIM_NFC_D (Data bus shared with NAND Flash) EIM_Dx (dedicated data bus) EIM_WAIT ) is Data propogation delay from I/O pad to Dpd Freescale Semiconductor ...
Page 51
... Setup MUM = 0, DSZ = 111 A[15:0] A[25:16] D[7:0], EIM_EB0 D[15:8], EIM_EB1 D[23:16], EIM_EB2 D[31:24], EIM_EB3 i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 36. EIM Internal Module Multiplexing Non Multiplexed Address/Data Mode 8 Bit 16 Bit MUM = 0, DSZ = 010 EIM_DA[15:0] EIM_DA[15:0] EIM_A[25:16] EIM_A[25:16] — ...
Page 52
... Address/Data mode 32 Bit 16 Bit 32 Bit MUM = 0, MUM = 1, MUM = 1, DSZ = 011 DSZ = 00 DSZ = 011 1 EIM_DA[15: EIM_DA[1 EIM_DA[15 0] 5:0] :0] EIM_A[24:1 EIM_A[ :16] NANDF_D[ 1 8:0] NANDF_D[ EIM_DA[7 EIM_DA[7: 7:0] :0] 0] NANDF_D[ EIM_DA[1 EIM_DA[15 15:8] 5:8] :8] EIM_D[23:1 — NANDF_D[ 6] 7:0] EIM_D[31:2 — NANDF_D[ 4] 15:8] Freescale Semiconductor ...
Page 53
... ID Parameter Min 2 WE1 BCLK Cycle time t WE2 BCLK Low Level 0.4*t Width i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor specify the timings related to the EIM module. All EIM output control WE2 WE1 WE4 WE6 WE8 WE10 WE12 WE14 WE16 Figure 16 ...
Page 54
... Freescale Semiconductor Max — — — — ...
Page 55
... BCLK ADDR Last Valid Address CSx_B WE_B ADV_B OE_B BEy_B DATA Figure 18. Synchronous Memory Read Access, WSC=1 i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor ≤ 104 MHz. If BCD = 1, then 133 MHz is WE4 Address v1 WE6 WE14 WE15 WE10 WE12 WE18 ...
Page 56
... Applications Processors for Consumer Products, Rev WE4 Address V1 WE6 WE8 WE14 WE15 WE12 WE16 WE16 WE5 WE4 Address V1 Last WE6 WE8 WE15 WE14 WE10 ADH=1 NOTE WE5 WE7 WE9 WE13 WE17 D(V1) WE17 Write Data WE7 WE9 WE11 Freescale Semiconductor ...
Page 57
... Asynchronous read & write access length in cycles may vary from what is shown in Figure 25 as RWSC, OEN & CSN is configured differently. Refer to i.MX53xDRM for the EIM pro- gramming model. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor WE4 WE5 Address V1 WE6 ...
Page 58
... Applications Processors for Consumer Products, Rev start of access WE31 Address V1 WE39 WE35 WE37 D(V1) WE43 MAXDI start of access MAXDI WE31 Addr. V1 WE32A WE40A WE39 WE35A WE37 end of access WE32 Next Address WE40 WE36 WE38 WE44 end of access D(V1) WE44 WE36 WE38 Freescale Semiconductor ...
Page 59
... Figure 24. Asynchronous Memory Write Access (RWSC = 5, OEN=CSN=0) CSx_B ADDR/ M_DATA WE_B ADV_B OE_B BEy_B Figure 25. Asynchronous A/D Muxed Write Access (RWSC = 5, OEN=CSN=0) i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor WE31 Address V1 WE33 WE39 WE45 D(V1) WE41 WE41 WE31 D(V1) Addr ...
Page 60
... Next Address WE40 WE36 WE38 WE44 WE48 Max (If 133 Mhz is Min supported by SOC) — CSA — CSN -3 + (ADVN + — ADVA + 1 - CSA) — (WEA - CSA) — (WEN_CSN) — (OEA - CSA (OEA + 3 + (OEA + RADVN+RADVA RADVN+RADVA+A +ADH+1-CSA) DH+1-CSA) — (OEN - CSN) Freescale Semiconductor Unit ...
Page 61
... WE45 CSx_B Valid to BEy_B Valid (Write access) WE46 BEy_B Invalid to CSx_B Invalid (Write access) i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Determination by Synchronous measured 12 parameters WE12 - WE6 + (RBEA - CSA) WE7 - WE13 + (RBEN - CSN) WE14 - WE6 + (ADVA - CSA) WE7 - WE15 - CSN ...
Page 62
... The LPDDR2 interface fully complies with JESD209-2B, supporting LPDDR2-800. i.MX53xD Applications Processors for Consumer Products, Rev Determination by Synchronous measured Min 12 parameters MAXCO - MAXCSO + MAXCO - MAXDTI MAXCSO + MAXDTI 0 Table 38 Max (If 133 Mhz is Unit supported by SOC) — — — — — ns Freescale Semiconductor ...
Page 63
... Figure 27. DDR SDRAM Basic Timing Parameters Figure 28 shows the write timing parameters. SDCLK SDCLK_B DDR21 DQS (output) DDR17 DQ (output) DQM (output) DDR17 i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor DDR4 DDR5 DDR4 DDR5 DDR4 DDR7 COL/BA DDR22 DDR18 DDR17 Data ...
Page 64
... NOTE DATA DATA DATA DATA DDR26 Table 40. CSPI Nomenclature and Routing GPIO, KPP, DISP0_DAT, CSI0_DAT and EIM_D through IOMUXC DISP0_DAT, CSI0_DAT and EIM through IOMUXC DISP0_DAT, EIM_A/D, SD1 and SD2 through IOMUXC DATA DATA DATA DATA Table 40. I/O Access Freescale Semiconductor ...
Page 65
... MISO Hold Time 2 CS10 RDY to SSx Time 1 See specific I/O AC parameters Section 4.5, “I SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 41 CS2 CS3 CS2 CS3 Symbol t clk t SW ...
Page 66
... LOAD PDmiso Table 43 lists the ECSPI master mode timing Symbol t clk RISE/FALL t CSLH CS5 CS6 CS4 Min Max Unit 100 — ns — ns — ns — ns — ns — ns — Min Max Unit 30 — — — — ns Half SCLK period — ns Freescale Semiconductor ...
Page 67
... The ESAI consists of independent transmitter and receiver sections, each section with its own clock generator. Table 45 shows the interface timing values. The number field in the table refers to timing signals found in Figure 32 and Figure 33. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Symbol t SCS t HCS = 20 pF) t LOAD PDmosi ...
Page 68
... Freescale Semiconductor 4 Unit ...
Page 69
... Periodically sampled and not 100% tested. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor 1 2,3 ’ Symbol Expression — ...
Page 70
... Electrical Characteristics 63 SCKT (Input/Output) FST (Bit) Out FST (Word) Out Data Out FST (Bit) In FST (Word) In i.MX53xD Applications Processors for Consumer Products, Rev First Bit Figure 32. ESAI Transmitter Timing 83 87 Last Bit 91 Freescale Semiconductor ...
Page 71
... SCKR (Input/Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor First Bit Figure 33. ESAI Receiver Timing Electrical Characteristics 70 72 Last Bit 75 71 ...
Page 72
... SCK SD3 CMD SD6 DAT0 DAT1 ...... DAT7 SD7 SD8 CMD DAT0 DAT1 ...... DAT7 Figure 34. SD/eMMC4.3 Timing Card Input Clock SD1 Symbols Min Max 400 25/ 20/ 100 400 — — — 3 TLH t — 3 THL t – Freescale Semiconductor Unit kHz MHz MHz kHz ...
Page 73
... Clock Frequency (MMC Full Speed/High Speed) eSDHC Output / Card Inputs CMD, DAT (Reference to CLK) SD2 eSDHC Output Delay eSDHC Input / Card Outputs CMD, DAT (Reference to CLK) i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor – 50 MHz. – 52 MHz. Table 47 lists the eMMC4.4 timing characteristics. Be aware ...
Page 74
... Applications Processors for Consumer Products, Rev Symbols t ISU t IH Table 48 lists the MII receive channel signal timing Table 48. MII Receive Signal Timing 1 2 Min Max Unit 2.5 — ns 2.5 — ns Min Max Unit 5 — — ns 35% 65% FEC_RX_CLK period 35% 65% FEC_RX_CLK period Freescale Semiconductor ...
Page 75
... FEC_TX_CLK pulse width high M8 FEC_TX_CLK pulse width low 1 FEC_TX_EN, FEC_TX_CLK, and FEC_TXD0 have the same timing in 10 Mbps 7-wire interface mode. 2 Test conditions: 25pF on each output signal. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Figure 37 Table 49. Table 49. MII Transmit Signal Timing ...
Page 76
... Table 50. MII Async Inputs Signal Timing 1 M9 Figure 38. MII Async Inputs Timing Diagram Figure 39 Table 51. MII Transmit Signal Timing 1 Characteristics M8 Figure 38 shows MII asynchronous Min Max Unit 1.5 — FEC_TX_CLK period shows MII serial management channel Min Max Unit 0 — ns — — ns Freescale Semiconductor ...
Page 77
... The RMII mode timings are shown in No. M16 REF_CLK(FEC_TX_CLK) pulse width high M17 REF_CLK(FEC_TX_CLK) pulse width low M18 REF_CLK to FEC_TXD[1:0], FEC_TX_EN invalid M19 REF_CLK to FEC_TXD[1:0], FEC_TX_EN valid i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor 1 Characteristics M14 M12 M13 Table 52 and Figure 40. Table 52. RMII Signal Timing ...
Page 78
... Tx and Rx pins; these ports are named TXCAN and RXCAN, respectively. i.MX53xD Applications Processors for Consumer Products, Rev Table 52. RMII Signal Timing (continued) 1 Characteristics M16 M18 M19 M20 M21 Min Max Unit 4 — — ns M17 Freescale Semiconductor ...
Page 79
... If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the I2CLK line is released total capacitance of one bus line in pF. b i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor 2 C module module timing characteristics. IC11 IC10 IC7 ...
Page 80
... Y[1] Y[1] G[5] Y[2] Y[2] R[0] Y[3] Y[3] R[1] Y[4] Y[4] R[2] Y[5] Y[5] R[3] Y[6] Y[6] R[4] Y[7] Y[7] Freescale Semiconductor 7 C[0] C[1] C[2] C[3] C[4] C[5] C[6] C[7] C[8] C[9] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Y[8] ...
Page 81
... Then SENSB_HSYNC goes to high and hold for the entire line. Pixel clock is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Active Line n+1th frame invalid ...
Page 82
... Applications Processors for Consumer Products, Rev Section 4.7.8.2.2, “Gated Clock n+1th frame 1st byte is that of a typical sensor. Some other sensors may have a slightly IP2 IP3 Figure 44. Sensor Interface Timing Diagram Figure 43). All incoming pixel clocks are invalid 1st byte 1/IP1 Freescale Semiconductor Mode,”) ...
Page 83
... Data and control holdup time 4.7.8.4 IPU Display Interface Signal Mapping The IPU supports a number of display output video formats. Interface Pins used during various supported video interface formats. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Electrical Characteristics Symbol Min Fpck 0.01 ...
Page 84
... Groups should not be overlapped. DAT[3] b) The bit order is expressed in DAT[4] each of the bit groups, for example B[0] = least significant blue pixel DAT[5] bit DAT[6] DAT[7] DAT[8] DAT[9] DAT[10] DAT[11] DAT[12] DAT[13] DAT[14] DAT[15] — — — — — — Freescale Semiconductor ...
Page 85
... This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data during blanking intervals is not supported. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor LCD 18-bit 24 Bit ...
Page 86
... When a DI decides to put a new asynchronous data in the bus, a new internal start (local start point) is generated. The signals generators calculate predefined UP and DOWN values to change pins states with half DI_CLK resolution. i.MX53xD Applications Processors for Consumer Products, Rev NOTE NOTE Freescale Semiconductor ...
Page 87
... VSYNC HSYNC LINE 1 HSYNC DRDY IPP_DISP_CLK IPP_DATA Figure 45. Interface Timing Diagram for TFT (Active Matrix) Panels i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor LINE 2 LINE 3 LINE Electrical Characteristics LINE n-1 LINE n m– ...
Page 88
... All parameters shown in the figure are programmable. IP13 VSYNC HSYNC DRDY IP11 Figure 47. TFT Panels Timing Diagram—Vertical Sync Pulse i.MX53xD Applications Processors for Consumer Products, Rev IP8o IP8 D0 IP9o IP9 IP6 Start of frame IP14 IP12 IP7 IP5 Dn D1 IP10 End of frame IP15 Freescale Semiconductor ...
Page 89
... IP10 Horizontal blank interval 2 IP12 Screen height IP13 VSYNC width IP14 Vertical blank interval 1 IP15 Vertical blank interval 2 i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Figure 46 Symbol Value 1 Tdicp ( ) Display interface clock. Tdpcp DISP_CLK_PER_PIXEL Time of translation of one pixel to display, × ...
Page 90
... DI’s counter. DRDY_OFFSET—offset of DRDY edges from a suitable local start point, when a corresponding data has been set on the × bus, in DI_CLK 2 (0.5 DI_CLK Resolution) The DRDY_OFFSET should be built by suitable DI’s counter. for integer DISP_CLK_PERIOD --------------------------------------------------- - DI_CLK_PERIOD for fractional DISP_CLK_PERIOD --------------------------------------------------- - DI_CLK_PERIOD Freescale Semiconductor Unit ...
Page 91
... The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be chip specific. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor ± Accuracy = T diclk 0.62ns ...
Page 92
... The active intervals—during which data is transferred—are marked by the HSYNC signal being high. i.MX53xD Applications Processors for Consumer Products, Rev × ⎛ 2 DISP_CLK_DOWN 1 × ---------------------------------------------------------- - Tdicd = -- - T diclk ceil ⎝ DI_CLK_PERIOD 2 × ⎛ 2 DISP_CLK_UP 1 × ----------------------------------------------- - Tdicu = -- - T diclk ceil ⎝ DI_CLK_PERIOD 2 49. NOTE ⎞ ⎠ ⎞ ⎠ Freescale Semiconductor ...
Page 93
... VSYNC 621 622 HSYNC DRDY VSYNC Even Field 308 309 HSYNC DRDY VSYNC Odd Field Figure 49. TV Encoder Interface Timing Diagram i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Pixel Data Timing 524 525 Even Field 262 263 264 265 ...
Page 94
... Degrees — 75 — dB — 0.8 — ±Degrees — 1.5 — ±% — –70 — dB — –47 — dB — 0.5 — ±Degrees — 2.5 — ±% — 0.1 — ±% — 1.0 — ±% Freescale Semiconductor ...
Page 95
... A pause between two different display accesses can be guaranteed by programing suitable access sizes. There are no minimal/maximal hold/setup times hard defined by DI. Each control signal can be switched at any time during access size. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Conditions — 2 ...
Page 96
... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 50. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram i.MX53xD Applications Processors for Consumer Products, Rev Burst access mode with sampling by CS signal Freescale Semiconductor ...
Page 97
... Burst access mode with sampling by WR/RD signals IPP_CS IPP_DATA Single access mode (all control signals are not active for one display interface clock after each display access) Figure 51. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Electrical Characteristics 97 ...
Page 98
... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 52. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram i.MX53xD Applications Processors for Consumer Products, Rev Burst access mode with sampling by CS signal Freescale Semiconductor ...
Page 99
... DI_CLK delay. The DI finishes a current access and a next access is postponed until IPP_WAIT release. Figure 54 shows timing of the parallel interface with IPP_WAIT control. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Burst access mode with sampling by ENABLE signal Electrical Characteristics 99 ...
Page 100
... Table 61 shows timing characteristics at display access level. All timing diagrams are based on active low control signals (signals polarity is controlled through the DI_DISP_SIG_POL register). i.MX53xD Applications Processors for Consumer Products, Rev. 1 100 waiting waiting Freescale Semiconductor ...
Page 101
... Address Write system cycle time Tcycwa IP28d Data Write system cycle time IP29 RS start IP30 CS start IP31 CS hold IP32 RS hold IP33 Read start i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor IP36 IP34 D1 IP28d Symbol Value Tcycr ACCESS_SIZE_# ACCESS_SIZE_# Tcycwd ACCESS_SIZE_# Tdcsrr UP# ...
Page 102
... Point of input data sampling by DI, predefined in DC Microcode 1 Max Tdicpr+1.24 Tdicpw+1.24 Tdicurs+1.24 Tdicucs+1.24 5 Tdicdcs – Tdicucs+1.24 7 Tdicdrs – Tdicurs+1.24 Tdicur+1.24 9 Tdicdr – Tdicur+1.24 Tdicuw+1.24 11 Tdicdw–Tdicuw+1. Tdrp – Tlbd –Tdicur–1. 24 Tdicpr – Tdicdr – 1.24 Freescale Semiconductor Unit — Unit ...
Page 103
... DISP_UP is predefined in REGISTER. 6 Display control down for RS DISP_DOWN is predefined in REGISTER. 7 Display control up for RS DISP_UP is predefined in REGISTER. 8 Display control down for read DISP_DOWN is predefined in REGISTER. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Min — Tdrp – 1.24 Tdrp DI_ACCESS_SIZE_# × ---------------------------------------------------- - Tdicpr = T DI_CLK ...
Page 104
... DISP_UP_# 1 × --------------------------------------------- - Tdicur = -- - T DI_CLK ceil ⎝ DI_CLK_PERIOD 2 × ⎛ 2 DISP_DOWN_# 1 × ------------------------------------------------- - = -- - T DI_CLK ceil ⎝ DI_CLK_PERIOD 2 × ⎛ 2 DISP_UP_# 1 × --------------------------------------------- - Tdicuw = -- - T DI_CLK ceil ⎝ DI_CLK_PERIOD 2 DISP#_READ_EN × --------------------------------------------- - Tdrp = T DI_CLK ceil DI_CLK_PERIOD ⎞ ⎠ ⎞ ⎠ ⎞ ⎠ Freescale Semiconductor ...
Page 105
... DISPB_D#_CS delay DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) programed DISPB_D#_CS delay DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) Figure 57. 4-Wire Serial Interface Timing Diagram i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Preamble Write Preamble Read RW RS Preamble D7 Electrical Characteristics programed delay ...
Page 106
... DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) programed DISPB_SER_RS delay Figure 58. 5-Wire Serial Interface Timing Diagram i.MX53xD Applications Processors for Consumer Products, Rev. 1 106 Write programed delay RW D7 Preamble Read programed delay RW Preamble D7 programed delay Output data programed delay Input data Freescale Semiconductor ...
Page 107
... IP48 Read system cycle time IP49 Write system cycle time IP50 Read clock low pulse width IP51 Read clock high pulse width Trh i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 62 shows timing characteristics at display access IP73 IP72 IP71 ...
Page 108
... Tdicpr – Tdicdr – 1.24 Tdicdw — Tdicpw – Tdicdw — Tdicpr Tdicpr+1.24 Tdicpw Tdicpw+1.24 Tdicdr Tdicdr+1.24 Tdicur Tdicur+1.24 Tdicdw Tdicdw+1.24 Tdicuw Tdicuw+1.24 Tdrp Tdrp+1.24 Toclk Toclk+1.24 Tdicurs Tdicurs+1.24 Tdicdrs Tdicdrs+1.24 Tdicucs Tdicucs+1.24 Tdicdcs Tdicdcs+1.24 Freescale Semiconductor Unit ...
Page 109
... Display interface clock offset value CLK_OFFSET is predefined in REGISTER. 12 Display RS up time DISP_RS_UP is predefined in REGISTER. 13 Display RS down time DISP_RS_DOWN is predefined in REGISTER. 14 Display RS up time DISP_CS_UP is predefined in REGISTER. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor × ⎛ 2 DISP_DOWN_# 1 × ------------------------------------------------- - Tdicdr = -- - T DI_CLK ceil ⎝ ...
Page 110
... RSTL Table 64 lists the timing parameters. OW6 OW5 One Wire Device Tx “Presence Pulse” OW4 Min Typ Max 1 480 511 — 15 — — 240 480 512 — should always be less than 960 µ REC Freescale Semiconductor Unit µs µs µs µs ...
Page 111
... Write 1 Low Time OW8 Transmission Time Slot Read Data Setup OW9 Read Low Time OW10 Read Data Valid OW11 Release Time i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Symbol t LOW0 t SLOT t REC Figure 63 depicts the Read Sequence timing, and OW8 ...
Page 112
... Applications Processors for Consumer Products, Rev. 1 112 Table 66 lists the PWM timing parameters Figure 64. PWM Timing Table 66. PWM Output Timing Parameter Min 1 0 12.29 9.91 — — — 8. Max ipg_clk — — 0.5 0.5 9.37 — Freescale Semiconductor Unit MHz ...
Page 113
... In the timing equations, some timing parameters are used. These parameters depend on the implementation of the i.MX53xD PATA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 68 shows ATA timing parameters. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor SI2 Parameter 1 1 – ...
Page 114
... UDMA2, UDMA3 UDMA0, UDMA1, UDMA2, UDMA3, UDMA4 Value/ 1 Contributing Factor Peripheral clock frequency (7.5 ns for 133 MHz clock) UDMA0 15 ns UDMA1 UDMA4 5 ns UDMA5 4 ns 5.0 ns UDMA5 4.6 ns 12.0 ns 8.5 ns 8 Transceiver Transceiver Transceiver Cable Cable Cable Cable Cable Freescale Semiconductor ...
Page 115
... T > tsu + thi + tskew3 + tskew4 t0 — t0(min) = (time_1 + time_2r+ time_9 i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 69 lists the timing parameters for PIO read. Figure 66. PIO Read Timing Diagram Table 69. PIO Read Timing Parameters Value ...
Page 116
... Applications Processors for Consumer Products, Rev. 1 116 Table 70 lists the timing parameters for PIO write. Figure 67. Multi-word DMA (MDMA) Timing Table 70. PIO Write Timing Parameters Value Controlling Variable time_1 time_2w time_9 If not met, increase time_2w time_4 time_ax time_1, time_2r, time_9 — — Freescale Semiconductor ...
Page 117
... T – (tskew1 + tskew2 + tskew6) tL — tL (max) = (time_d + time_k – 2) i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Figure 69 shows timing for MDMA write, and Figure 68. MDMA Read Timing Diagram Figure 69. MDMA Write Timing Diagram Value × ...
Page 118
... Applications Processors for Consumer Products, Rev. 1 118 Value × T – tskew1 × T – tskew1 and Figure 69) equals (tk – 2*T). Figure 71 shows timing when the UDMA in device terminates transfer, and Controlling Variable time_jn — shows timing when the UDMA in Freescale Semiconductor ...
Page 119
... Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 72. UDMA in Burst Timing Parameters Description × T) – (tskew1 + tskew2) × T) – (tskew1 + tskew2) × ...
Page 120
... T) – (tskew1 + tskew2) × T – tskew1 × T – tskew1 Figure 74 shows timing when the UDMA out device terminates transfer, and Controlling Variable T big enough time_rp tcable2) > trfs (drive) time_rp time_mlix time_zah time_dzfs time_cvh — shows timing when the UDMA out Freescale Semiconductor ...
Page 121
... Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Value × T) – (tskew1 + tskew2) × T) – (tskew1 + tskew2) × (tskew1 + tskew2) × T) – (tskew1 + tskew2) × T) – (tskew1 + tskew2) × ...
Page 122
... Test Conditions — — For information about total phase jitter, see following section — — Controlling Variable — time_dzfs time_ss T – (tskew1 + tskew2) — — — — time_cvh — Min Max 350 850 175 2,000 — 156.25 Freescale Semiconductor Unit RMS % UI MHz ...
Page 123
... Table 75 provides specifications for SATA PHY transmitter characteristics. Table 75. SATA2 PHY Transmitter Characteristics Parameters Transmit common mode voltage Transmitter pre-emphasis accuracy (measured change in de-emphasized bit) i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor NOTE Symbol Min V 0.4 CTM — –0.5 ...
Page 124
... MHz to 156.25 MHz. SATA_REXT does not need to be connected, as the termination impedance is not of consequence. i.MX53xD Applications Processors for Consumer Products, Rev. 1 124 Symbol Min — MIN_RX_EYE_HEIGHT PPM –400 NOTE Typ Max Unit — 175 mV — 400 ppm Ω. 1% precision resistor Freescale Semiconductor ...
Page 125
... Data Inputs Data Outputs Data Outputs Data Outputs Figure 78. Boundary Scan (JTAG) Timing Diagram i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Figure 78 depicts the SJC boundary scan timing. SJ1 SJ2 VM VIH VIL Figure 77. Test Clock Input Timing Diagram SJ4 ...
Page 126
... Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid SJ13 Figure 80. TRST Timing Diagram Table 77. JTAG Timing 1,2 Parameter VIH SJ9 All Frequencies Unit Min Max 0.001 22 MHz 45 — ns 22.5 — ns — — — ns — — — ns Freescale Semiconductor ...
Page 127
... Modulating Rx clock (SRCK) period SRCK high period SRCK low period Modulating Tx clock (STCLK) period STCLK high period STCLK low period i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 77. JTAG Timing (continued) 1,2 Parameter Table 78. SPDIF Timing Parameters Symbol — ...
Page 128
... Type and Access SSI 1 Internal SSI 2 Internal AUD3 External – AUD3 I/O AUD4 External – EIM or CSPI1 I/O through IOMUXC AUD5 External – EIM or SD1 I/O through IOMUXC AUD6 External – EIM or DISP2 through IOMUXC SSI 3 Internal NOTE M M Freescale Semiconductor ...
Page 129
... SS12 (Tx) CK high to FS (wl) low SS14 (Tx/Rx) Internal FS rise time SS15 (Tx/Rx) Internal FS fall time SS16 (Tx) CK high to STXD valid from high impedance i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 80 SS1 SS5 SS4 SS8 SS10 SS14 SS16 SS17 ...
Page 130
... Tx Data (for example, during AC97 mode of operation). i.MX53xD Applications Processors for Consumer Products, Rev. 1 130 Parameter Synchronous Internal Clock Operation NOTE Min Max Unit — 15.0 ns — 15.0 ns — 6.0 ns 10.0 — ns 0.0 — ns — 25.0 pF Freescale Semiconductor ...
Page 131
... SS11 (Rx) CK high to FS (wl) high SS13 (Rx) CK high to FS (wl) low SS20 SRXD setup time before (Rx) CK low SS21 SRXD hold time after (Rx) CK low i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 81 SS1 SS5 SS4 SS9 SS11 SS20 SS51 ...
Page 132
... For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX53xD Applications Processors for Consumer Products, Rev. 1 132 Parameter Oversampling Clock Operation NOTE Min Max Unit 15.04 — ns 6.0 — ns — 3.0 ns 6.0 — ns — 3.0 ns Freescale Semiconductor ...
Page 133
... SS31 (Tx) CK high to FS (wl) high SS33 (Tx) CK high to FS (wl) low SS37 (Tx) CK high to STXD valid from high impedance SS38 (Tx) CK high to STXD high/low i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 82 SS22 SS25 SS26 SS27 SS29 SS31 SS37 SS44 ...
Page 134
... For internal Frame Sync operation using external clock, the FS timing is same as that of Tx Data (for example, during AC97 mode of operation). i.MX53xD Applications Processors for Consumer Products, Rev. 1 134 Parameter Synchronous External Clock Operation NOTE Min Max Unit — 15.0 ns 10.0 — ns 2.0 — ns — 6.0 ns Freescale Semiconductor ...
Page 135
... SS35 (Tx/Rx) External FS rise time SS36 (Tx/Rx) External FS fall time SS40 SRXD setup time before (Rx) CK low SS41 SRXD hold time after (Rx) CK low i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Table 83 SS22 SS26 SS25 SS28 SS30 SS32 SS35 ...
Page 136
... Input RTS from DTE to DCE Output CTS from DCE to DTE Input DTR from DTE to DCE Output DSR from DCE to DTE DCD from DCE to DTE RING from DCE to DTE Serial data from DCE to DTE Input Serial data from DTE to DCE Freescale Semiconductor ...
Page 137
... The following subsections give the UART transmit and receive timings in IrDA mode. 4.7.17.3.3 UART IrDA Mode Transmitter Figure 89 depicts the UART IrDA mode transmit timing, with 8 data bit/1 stop bit format. the transmit timing characteristics. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor UA1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 ...
Page 138
... T T ref_clk ref_clk Table 88 UA6 UA5 UA5 Possible Bit 5 Bit 6 Bit 7 Parity Bit Min Max 2 1/F – 1/F + baud_rate baud_rate ) 1/(16*F ) baud_rate baud_rate 1.41 us (5/16)*(1/F baud_rate Freescale Semiconductor STOP BIT Units — — lists the STOP BIT Units — ) — ...
Page 139
... Transmit USB_TXOE_B USB_DAT_VP USB_SE0_VM Figure 91. USB Transmit Waveform in DAT_SE0 Bidirectional Mode i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Parameters.” Direction Transmit enable, active low TX data when USB_TXOE_B is low Differential RX data when USB_TXOE_B is high SE0 drive when USB_TXOE_B is low ...
Page 140
... RX Rise/Fall Time USB_SE0_VM i.MX53xD Applications Processors for Consumer Products, Rev. 1 140 US7 Signal Name Direction Min USB_DAT_VP Out -— Out — Out — USB_DAT_VP Out 49.0 USB_DAT_VP In — In — US8 Conditions / Max Unit Reference Signal 51.0 % — Freescale Semiconductor ...
Page 141
... USB_SE0_VM USB_VP1 USB_VM1 Transmit USB_TXOE_B USB_DAT_VP USB_SE0_VM Figure 93. USB Transmit Waveform in DAT_SE0 Unidirectional Mode i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Direction Out Transmit enable, active low Out TX data when USB_TXOE_B is low Out SE0 drive when USB_TXOE_B is low In Buffered data on DP when USB_TXOE_B is high ...
Page 142
... RX Rise/Fall Time US16 RX Rise/Fall Time i.MX53xD Applications Processors for Consumer Products, Rev. 1 142 US15 Signal Min Source Out — Out — Out — Out 49.0 USB_VP1 In — USB_VM1 In — US16 Condition / Max Unit Reference Signal 51.0 % — Freescale Semiconductor ...
Page 143
... US21 Figure 95. USB Transmit Waveform in VP_VM Bidirectional Mode Receive USB_DAT_VP USB_SE0_VM Figure 96. USB Receive Waveform in VP_VM Bidirectional Mode i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Direction Out Transmit enable, active low Out (Tx data when USB_TXOE_B is low In (Rx data when USB_TXOE_B is high ...
Page 144
... Signal Name Direction Min USB_DAT_V Out — P USB_SE0_V Out — M USB_TXOE Out — _B USB_DAT_V Out 49.0 P USB_SE0_V Out -3.0 M USB_DAT_V In — P USB_SE0_V In — M USB_DAT_V In -4.0 P Condition / Max Unit Reference Signal 51.0 % — +3.0 ns USB_DAT_VP 3 3 +4.0 ns USB_SE0_VM Freescale Semiconductor ...
Page 145
... USB_VP1 USB_VM1 Transmit USB_TXOE_B USB_DAT_VP USB_SE0_VM US33 Figure 97. USB Transmit Waveform in VP_VM Unidirectional Mode i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Direction Out Transmit enable, active low Out TX VP data when USB_TXOE_B is low Out TX VM data when USB_TXOE_B is low In ...
Page 146
... US40 US39 Signal Direction Min USB_DAT_VP Out — USB_SE0_V Out — M USB_TXOE_ Out — B USB_DAT_VP Out 49.0 USB_SE0_V Out -3.0 M USB_VP1 In — USB_VM1 In — USB_VP1 In -4.0 Conditions / Max Unit Reference Signal 51.0 % — 3.0 ns USB_DAT_VP 3 3 +4.0 ns USB_VM1 Freescale Semiconductor ...
Page 147
... This section describes the USB-OTG PHY and the USB Host port PHY parameters. 4.7.19.1 USB PHY AC Parameters Table 99 lists the AC timing parameters for USB PHY. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Direction In Interface clock. All interface signals are synchronous to Clock. Bi-directional data bus, driven low by the link during idle. Bus I/O ownership is determined by Dir ...
Page 148
... All conditions Min Typ –150 — — — 0 — 0 — 40 — Max Unit 300 ns 20 300 0.2 Min Typ Max Unit –0.05 — 0.5 V 0.8 2.5 1.3 — 1.3 2 – – – – Max Unit 150 ppm 200 100 Freescale Semiconductor ...
Page 149
... Parameter Min Frequency 1 Recommended nominal frequency 32.768 kHz. Table 105 shows the CKIL electrical specifications. Parameter Min Frequency 16 i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor VBUS Table 102. Comparators Thresholds Conditions Min — 0.8 — 0.8 — 0.2 — ...
Page 150
... Applications Processors for Consumer Products, Rev. 1 150 Symbol Min V 1.15 VID_DIG_PLL V 1.7 VDD_ANA_PLL — — — — — — — VID_DIG_PLL I VDD_ANA_PLL E-Fuse Name N/A Typ Max Units 1.2 1.3 V 1.8 1.95 V — +/–3 % –18 — dB –15 — dB — 125 mA Details Boot Mode selection Freescale Semiconductor ...
Page 151
... SPI CSPI EIM_A25, EIM_D21, EIM_D22, EIM_D28 SPI ECSPI-1 EIM_D[19:16] SPI ECSPI-2 CSI_DAT[10:8], EIM_LBA i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor E-Fuse Name BOOT_CFG1[7]/Test Mode Selection BOOT_CFG1[6]/Test Mode Selection BOOT_CFG1[5]/Test Mode Selection BOOT_CFG1[4] BOOT_CFG1[3] BOOT_CFG1[2] BOOT_CFG1[1] BOOT_CFG1[0] ...
Page 152
... NAND data can be muxed either over EIM data or PATA data • Only CS0 is supported bit bit bit bit — — — — — RXD/TXD only RXD/TXD only RXD/TXD only RXD/TXD only RXD/TXD only — 6), LDO output to VDD_DIG_PLL Freescale Semiconductor ...
Page 153
... Figure 100 shows the top view of the 19×19 mm package, location (529 solder balls) of the 19×19 mm package, and mm package. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Figure 101 Figure 102 Figure 100 Package Top View Package Information and Contact Assignments shows the bottom view and the ball shows the side view of the 19× ...
Page 154
... Package Information and Contact Assignments Figure 101 Package, 529 Solder Balls, Bottom View i.MX53xD Applications Processors for Consumer Products, Rev. 1 154 Figure 102 Package Side View Freescale Semiconductor ...
Page 155
... U13 NVCC_LVDS_BG U14 NVCC_NANDF T12 NVCC_PATA N7 NVCC_RESET H16 NVCC_SD1 H15 i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 100, Figure 101, and Figure 102. Table 111 shows the package ball map. Package Pin Assignment(s) 155 ...
Page 156
... G10, G11, G8, H11, H7, H9, J10, J12, J8, K11, K7, K9, L10, L12, L8 VDD_REG G18 VP A15, B15 VPH A9, B9 Table 110 displays an alpha-sorted list of the signal assignments including power rails. The table also includes out of reset pad state. i.MX53xD Applications Processors for Consumer Products, Rev. 1 156 Package Pin Assignment(s) Freescale Semiconductor ...
Page 157
... R4 NVCC_CSI CSI0_DATA_E P3 NVCC_CSI N CSI0_MCLK P2 NVCC_CSI CSI0_PIXCLK P1 NVCC_CSI CSI0_VSYNC P4 NVCC_CSI i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode LVIO ALT0 SRC src_BOOT_MOD E[0] LVIO ALT0 SRC ...
Page 158
... Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PD Input 100 KΩ PD Input 100 KΩ PD Input 100 KΩ PD Input 100 KΩ PD Input 100 KΩ PU Freescale Semiconductor ...
Page 159
... NVCC_EMI_DRAM RATION DRAM_CAS L18 NVCC_EMI_DRAM DRAM_CS0 K18 NVCC_EMI_DRAM DRAM_CS1 P19 NVCC_EMI_DRAM i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode GPIO ALT1 GPIO-4 gpio4_GPIO[30] DDR3 ALT0 ...
Page 160
... Value Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Output High Freescale Semiconductor ...
Page 161
... NVCC_EMI_DRAM DRAM_RESE P18 NVCC_EMI_DRAM T DRAM_SDBA R19 NVCC_EMI_DRAM 0 DRAM_SDBA P20 NVCC_EMI_DRAM 1 i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode DDR3 ALT0 EXTMC emi_DRAM_D[26 ] DDR3 ALT0 EXTMC emi_DRAM_D[27 ...
Page 162
... Directio Config./ n Value Output Low Output Low Output Low Output Floating Output Floating Output Floating Output Floating Output Low Output Low Input Low Input High Input Low Input High Input Low Input High Input Low Input High Output High Freescale Semiconductor ...
Page 163
... V5 NVCC_EIM_SEC EIM_D27 V4 NVCC_EIM_SEC EIM_D28 AA1 NVCC_EIM_SEC EIM_D29 AA2 NVCC_EIM_SEC i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode ANALOG — SRTC ECKIL {no block I/O by this name ...
Page 164
... KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ Input 100 KΩ Input 100 KΩ Input 100 KΩ Input 100 KΩ Input 100 KΩ Input 100 KΩ Input 100 KΩ Input 100 KΩ Output — Freescale Semiconductor ...
Page 165
... GPIO_10 W16 TVDAC_AHVDDRG B GPIO_11 V17 TVDAC_AHVDDRG B GPIO_12 W17 TVDAC_AHVDDRG B i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode UHVIO ALT0 EXTMC emi_EIM_EB[1] UHVIO ALT1 GPIO-2 gpio2_GPIO[30] ...
Page 166
... KΩ PU Input 100 KΩ PD Input 47 KΩ PU Input Keeper Input 47 KΩ PU Input 47 KΩ Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 360 KΩ PD Input 100 KΩ PU Input 100 KΩ PU Freescale Semiconductor ...
Page 167
... AC13 NVCC_LVDS N LVDS1_TX1_P AB13 NVCC_LVDS LVDS1_TX2_ AC12 NVCC_LVDS N LVDS1_TX2_P AB12 NVCC_LVDS i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode UHVIO ALT1 GPIO-4 gpio4_GPIO[13] UHVIO ALT1 ...
Page 168
... Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Freescale Semiconductor ...
Page 169
... A12 VPH SATA_RXP B12 VPH SATA_TXM B10 VPH SATA_TXP A10 VPH i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt. Block I/O Mode UHVIO ALT1 GPIO-2 gpio2_GPIO[2] UHVIO ALT1 ...
Page 170
... Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PU Input 100 KΩ PD — — — — — — — — — — — — — — — — — — Freescale Semiconductor ...
Page 171
... During power-on reset this port acts as output for diagnostic signal ANY_PU_RST KEY_COL0 and GPIO_19 act as output for diagnostic signals during power-on reset. i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Out of Reset Condition I/O Buffer Type Alt ...
Page 172
... Package Information and Contact Assignments 6 mm, 0.8 Pitch Ball Map shows the 19 × 19 mm, 0.8 pitch ball map. Table 111 i.MX53xD Applications Processors for Consumer Products, Rev. 1 172 Table 111 mm, 0.8 Pitch Ball Map Freescale Semiconductor ...
Page 173
... Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Table 111 mm, 0.8 Pitch Ball Map 173 ...
Page 174
... Package Information and Contact Assignments i.MX53xD Applications Processors for Consumer Products, Rev. 1 174 Table 111 mm, 0.8 Pitch Ball Map Freescale Semiconductor ...
Page 175
... Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Table 111 mm, 0.8 Pitch Ball Map 175 ...
Page 176
... Applications Processors for Consumer Products, Rev. 1 176 Figure 104 Figure 105 Figure 103. 12x12 mm PoP Top View shows the bottom view and the ball shows the side view of the 12×12 Freescale Semiconductor ...
Page 177
... Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Figure 104 PoP, Bottom View Package Information and Contact Assignments 177 ...
Page 178
... The table also includes out of reset pad state. i.MX53xD Applications Processors for Consumer Products, Rev. 1 178 Figure 105 PoP, Side View 103, Figure 104, and Figure – 1994. Table 115 and Table 116 105. show the package ball maps. Freescale Semiconductor ...
Page 179
... NVCC_PATA N6 NVCC_RESET AD18 NVCC_SD1 AC20 NVCC_SD2 AC16 NVCC_SRTC_POW F13 NVCC_XTAL F14 POP_VACC AG14 POP_VCCMM C8, L3 POP_VCCQMM C11 POP_VCCQMM1 H3 POP_VDD1 C3, C13, C26, T3, T27, AG6, AG26 i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments Contact Assignment 179 ...
Page 180
... Contact Name DDR_VREF GND POP_VACC i.MX53xD Applications Processors for Consumer Products, Rev. 1 180 Contact Assignment Contact Assignment P2, M22 A12, A15, A18, A21, B5, B8, B10, C1, C23, F2, F23, J2, J23, M2, M23, P23, R1, U23, V1, Y23,AA1, AB7, AB11, AC5, AC9, AC12, AC15, AC18, AC21 AC11 Freescale Semiconductor ...
Page 181
... T1 — CSI0_DAT15 P1 — CSI0_DAT16 M1 — i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Contact Assignment A6 A11, A20, B3, N2, N22,AB5, AC20 B11, B21, C2, L22, R2, AA2, AB10, AB21 U2, W2, AC8 AC10 B13, B16, B19, D22, G22, K22, R22, V22, AA22, AB13, AB16, AB19 ...
Page 182
... Input gpio5_GPIO[8] Input gpio5_GPIO[9] Input gpio5_GPIO[10] Input gpio5_GPIO[11] Input gpio5_GPIO[12] Input gpio5_GPIO[13] Input Freescale Semiconductor Config./ Value 360 KΩ PD 360 KΩ PD 360 KΩ PD 100 KΩ PU 360 KΩ PD 100 KΩ PU 100 KΩ PU 100 KΩ PU 360 KΩ PD 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ ...
Page 183
... W1 DRAM_A6 P23 V2 DRAM_A7 N23 U1 DRAM_A8 M24 T2 DRAM_A9 T23 T1 DRAM_CALIBR R23 — ATION i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor I/O Buffer Power Rail Type Mode NVCC_LCD GPIO ALT1 NVCC_LCD GPIO ALT1 NVCC_LCD GPIO ALT1 NVCC_LCD GPIO ALT1 NVCC_LCD GPIO ...
Page 184
... Output High emi_DRAM_D[22] Output High emi_DRAM_D[23] Output High emi_DRAM_D[24] Output High emi_DRAM_D[25] Output High emi_DRAM_D[26] Output High emi_DRAM_D[27] Output High emi_DRAM_D[28] Output High emi_DRAM_D[29] Output High emi_DRAM_D[3] Output High emi_DRAM_D[30] Output High emi_DRAM_D[31] Output High emi_DRAM_D[4] Output High Freescale Semiconductor Config./ Value ...
Page 185
... DRAM_SDCLK_ — 0_B DRAM_SDCLK_ H23 Y2 1 DRAM_SDCLK_ J23 Y1 1_B DRAM_SDODT L29 — 0 i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor I/O Buffer Power Rail Type Mode NVCC_EMI_DRAM DDR3 ALT0 NVCC_EMI_DRAM DDR3 ALT0 NVCC_EMI_DRAM DDR3 ALT0 NVCC_EMI_DRAM DDR3 ALT0 NVCC_EMI_DRAM ...
Page 186
... Output 2 emi_EIM_A[17] Output 2 emi_EIM_A[18] Output 2 emi_EIM_A[19] Output 2 emi_EIM_A[20] Output 2 emi_EIM_A[21] Output 2 emi_EIM_A[22] Output 2 emi_EIM_A[23] Output — emi_EIM_A[24] Output — Freescale Semiconductor Config./ Value Low High Low High Low High Low High — — — — — — — — ...
Page 187
... K1 — EIM_DA1 G11 — EIM_DA10 L7 — EIM_DA11 K7 — EIM_DA12 E2 D1 EIM_DA13 F2 E1 i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor I/O Buffer Power Rail Type Mode NVCC_EIM_MAIN UHVIO ALT0 NVCC_EIM_MAIN UHVIO ALT0 NVCC_EIM_MAIN UHVIO ALT0 NVCC_EIM_MAIN UHVIO ALT0 NVCC_EIM_SEC UHVIO ...
Page 188
... Output — emi_EIM_RW Output — emi_EIM_WAIT Output — EXTAL — FASTR_ANA — FASTR_DIG — gpio1_GPIO[25] Input Freescale Semiconductor Config./ Value 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU — ...
Page 189
... GPIO_4 AH11 — GPIO_5 AJ11 — GPIO_6 AJ12 — GPIO_7 AC11 — GPIO_8 AD10 — i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor I/O Buffer Power Rail Type Mode NVCC_FEC UHVIO ALT1 NVCC_FEC UHVIO ALT1 NVCC_FEC UHVIO ALT1 NVCC_FEC UHVIO ...
Page 190
... Input gpio7_GPI[28] Input gpio7_GPI[27] Input gpio7_GPI[26] Input gpio7_GPI[23] Input gpio7_GPI[22] Input gpio6_GPI[27] Input gpio6_GPI[26] Input Freescale Semiconductor Config./ Value 100 KΩ PU 100 KΩ PU 100 KΩ KΩ PU Keeper 47 KΩ KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 360 KΩ PD 100 KΩ ...
Page 191
... PATA_DA_2 Y3 — PATA_DATA0 B9 A7 PATA_DATA1 B8 B6 PATA_DATA10 B10 A8 PATA_DATA11 C9 B7 PATA_DATA12 Y1 — i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor I/O Buffer Power Rail Type Mode NVCC_LVDS LVDS ALT0 NVCC_LVDS LVDS ALT0 NVCC_LVDS LVDS ALT0 NVCC_LVDS LVDS ALT0 NVCC_LVDS LVDS ...
Page 192
... Input SATA_REFCLKM — SATA_REFCLKP — SATA_REXT — SATA_RXM — SATA_RXP — SATA_TXM — Freescale Semiconductor Config./ Value 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ PU 100 KΩ ...
Page 193
... TVDAC_IOB A23 — TVDAC_IOG B24 — TVDAC_IOR C29 — USB_H1_DN AH21 — USB_H1_DP AJ21 — i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor I/O Buffer Power Rail Type Mode VPH ANALOG — NVCC_SD1 UHVIO ALT1 NVCC_SD1 UHVIO ALT1 NVCC_SD1 UHVIO ...
Page 194
... Out of Reset Condition Alt. Direct Function ion USB_H1_GPANAIO — USB_H1_RREFEX — T USB_H1_VBUS — USB_OTG_DN — USB_OTG_DP — USB_OTG_GPANAI — O USB_OTG_ID — USB_OTG_RREFE — XT USB_OTG_VBUS — XTAL — Freescale Semiconductor Config./ Value — — — — — — — — — — Section 5.1, ...
Page 195
... Table 115. PoP 12 × 12 mm, 0.4 Pitch Top Ball Map i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 195 ...
Page 196
... Package Information and Contact Assignments Table 115. PoP 12 × 12 mm, 0.4 Pitch Top Ball Map (continued) i.MX53xD Applications Processors for Consumer Products, Rev. 1 196 Freescale Semiconductor ...
Page 197
... Table 115. PoP 12 × 12 mm, 0.4 Pitch Top Ball Map (continued) i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 197 ...
Page 198
... Package Information and Contact Assignments Table 116. PoP 12 × 12 mm, 0.4 Pitch Bottom Ball Map i.MX53xD Applications Processors for Consumer Products, Rev. 1 198 Freescale Semiconductor ...
Page 199
... Table 116. PoP 12 × 12 mm, 0.4 Pitch Bottom Ball Map (continued) i.MX53xD Applications Processors for Consumer Products, Rev. 1 Freescale Semiconductor Package Information and Contact Assignments 199 ...
Page 200
... Package Information and Contact Assignments Table 116. PoP 12 × 12 mm, 0.4 Pitch Bottom Ball Map (continued) i.MX53xD Applications Processors for Consumer Products, Rev. 1 200 Freescale Semiconductor ...