DS26518GNB1+ Maxim Integrated Products, DS26518GNB1+ Datasheet - Page 74
![IC TXRX T1/E1/J1 8PRT 256-CSBGA](/photos/6/50/65053/256-csbga_21-0315_sml.jpg)
DS26518GNB1+
Manufacturer Part Number
DS26518GNB1+
Description
IC TXRX T1/E1/J1 8PRT 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS26518GNB1.pdf
(312 pages)
Specifications of DS26518GNB1+
Number Of Drivers/receivers
8/8
Protocol
T1/E1/J1
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 74 of 312
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9.10
There are two HDLC controllers available for each port of the DS26518. HDLC-64 is the default HDLC controller,
which is software compatible to the entire TEX series of SCTs. The HDLC-256 controller is available on the
DS26518 beginning with die revision B1. (Note: Older DS26518 die revisions do not have this feature, so check
the device errata.)
Table 9-36. HDLC-64/HDLC-256 Controller Features
9.10.1 HDLC-64 Controller
The DS26518 has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1
mode), or the FDL (T1 mode). This HDLC controller has a 64-byte FIFO buffer in both the transmit and receive
paths. The user can select any specific bits within the time slot(s) to assign to the HDLC-64 controller, as well as
specific Sa bits (E1 mode).
The HDLC-64 controller performs all the necessary overhead for generating and receiving performance report
messages (PRMs) as described in ANSI T1.403 and the messages as described in AT&T TR54016. The HDLC-64
controller automatically generates and detects flags, generates and checks the CRC checksum, generates and
detects abort sequences, stuffs and destuffs zeros, and byte aligns to the data stream. The 64-byte buffers in the
HDLC-64 controller are large enough to allow a full PRM to be received or transmitted without host intervention.
Table 9-37
CONTROLLER
HDLC-256
HDLC-64
HDLC
HDLC Controllers
shows the registers related to the HDLC-64.
Table 9-36
FIFO DEPTH
(BYTES)
256
64
describes the features available for each controller.
MAP TO FDL
Yes
Yes
74 of 312
MAP TO
Sa BITS
Yes
Yes
SINGLE DS0
MAP TO
Yes
Yes
Yes, up to 32
MULTIPLE
MAP TO
DS0s
No
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