DS26334GA3+ Maxim Integrated Products, DS26334GA3+ Datasheet - Page 66
DS26334GA3+
Manufacturer Part Number
DS26334GA3+
Description
IC LIU E1/T1/J1 3.3V 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Line Interface Units (LIUs)r
Datasheet
1.DS26334G.pdf
(121 pages)
Specifications of DS26334GA3+
Number Of Drivers/receivers
16/16
Protocol
IEEE 1149.1
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.1.3 Individual LIU Register Bank
The ADDP register must be set to 01h to access this bank.
Register Name:
Register Description:
Register Address (LIUs 1–8):
Bit #
Name
Default
Register Address (LIUs 9–16):
Bit #
Name
Default
Bits 7 to 0: Individual Jitter Attenuator Enable Channel n (IJAEn). When this bit is set, the LIU jitter attenuator
n is enabled. Note that if the GC.JAE register bit is set, this register will be ignored.
Register Name:
Register Description:
Register Address (LIUs 1–8):
Bit #
Name
Default
Register Address (LIUs 9–16):
Bit #
Name
Default
Bits 7 to 0: Individual Jitter Attenuator Position Select Channel n (IJAPSn). When this bit is set high, the jitter
attenuator is in the receive path n; when this bit is default or set low the jitter attenuator is in the transmit path n.
Note that if the GC.JAE register bit is set, this register will be ignored.
IJAPS16
IJAPS8
IJAE16
IJAE8
7
0
7
0
7
0
7
0
IJAPS15
IJAPS7
IJAE15
IJAE7
6
0
6
0
6
0
6
0
IJAE
Individual Jitter Attenuator Enable Register
00h
20h
IJAPS
Individual Jitter Attenuator Position Select Register
01h
21h
IJAPS14
IJAPS6
IJAE14
IJAE6
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5
0
5
0
5
0
5
0
IJAPS13
IJAPS5
IJAE13
IJAE5
66 of 121
4
0
4
0
4
0
4
0
IJAPS12
IJAPS4
IJAE12
IJAE4
3
0
3
0
3
0
3
0
IJAPS11
IJAE11
IJAPS3
IJAE3
2
0
2
0
2
0
2
0
IJAPS10
IJAE10
IJAPS2
IJAE2
1
0
1
0
1
0
1
0
IJAPS1
IJAPS9
IJAE1
IJAE9
0
0
0
0
0
0
0
0
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