SAF7118EH/V1/G,557 Trident Microsystems, Inc., SAF7118EH/V1/G,557 Datasheet - Page 91
SAF7118EH/V1/G,557
Manufacturer Part Number
SAF7118EH/V1/G,557
Description
Manufacturer
Trident Microsystems, Inc.
Datasheet
1.SAF7118EHV1G557.pdf
(175 pages)
Specifications of SAF7118EH/V1/G,557
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Table 38.
Table 39.
[1]
SAF7118_4
Product data sheet
Function
Chip Version (CV)
Bit
D6
D[5:4]
D[3:0]
HLNRS = 1 should not be used in combination with WPOFF = 0.
Description
white peak control off
update hysteresis for 9-bit
gain; see
increment delay
Chip Version (CV) identification; 00h[7:4]; read only register
Horizontal increment delay; 01h[6:0]
10.2.1 Subaddress 00h
10.2.2 Subaddress 01h
10.2 I
Figure 9
The programming of the horizontal increment delay is used to match internal processing
delays to the delay of the ADC. Use recommended position only.
Logic levels
ID7
CV3
2
C-bus details
Symbol
WPOFF
GUDL[1:0]
IDEL[3:0]
ID6
CV2
[1]
Rev. 04 — 4 July 2008
Multistandard video decoder with adaptive comb filter
Value
0
1
00
01
10
11
1111
1110
0111
0000
ID5
CV1
Function
white peak control active (ADC signal is
attenuated, if nominal luminance output
white level is exceeded)
white peak control disabled
off
no update
minimum delay
recommended position
maximum delay
1 LSB
2 LSB
3 LSB
ID4
CV0
SAF7118
© NXP B.V. 2008. All rights reserved.
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