ST7540 STMicroelectronics, ST7540 Datasheet
ST7540
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ST7540 Summary of contents
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... September 2006 FSK power line transceiver = 5mA) Description q The ST7540 is a Half Duplex synchronous/asynchronous FSK Modem designed for power line communication network applications. It operates from a single supply voltage and integrates a line driver and two linear regulators for 5V and 3.3V. The device operation ...
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... Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Crystal resonator and external clock . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Carrier frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 Baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 Mark and space frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 ST7540 Mains access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5 Host processor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5.1 6.5.2 6.6 Receiving mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7 Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.8 Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2/44 Communication between Host and ST7540 ...
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... ST7540 7 Auxiliary analog and digital functions . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 Band in use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 Time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 Reset & watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.4 Output clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.5 Output voltage level freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.6 Extended control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.7 Under voltage lock out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.8 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.9 5V Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.10 3.3V Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7 ...
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... Block diagram 1 Block diagram Figure 1. Block diagram 4/44 ST7540 ...
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... ST7540 2 Pin settings 2.1 Pin connection Figure 2. Pin connection (top view) 2.2 Pin description Table 1. Pin description N° Name 1 CD_PD 2 REG_DATA 3 GND 4 RxD 5 RxTx 6 TxD 1 CD_PD 2 REG_DATA GND 3 4 RxD RxTx 5 6 TxD BU/THERM 7 CLR MCLK 11 RSTO 12 UART/SPI PA_IN- Type Carrier, preamble or frame header detect output. ...
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... A resistor between CL and SV Analog/Input limiting value. An integrated 80pF filtering input capacitance is present on this pin. Analog/Input Receiving analog input Power 5V voltage regulator output Digital/Input Test input. Must be connected to GND. with internal pull-down Test input. Must be connected SV Analog/Input ST7540 Description sets the PLI current SS SS ...
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... ST7540 3 Electrical data 3.1 Maximum ratings Table 2. Absolute maximum ratings Symbol V Power supply voltage CC V Digital supply voltage DD SV /GND Voltage between Digital input voltage I V Digital output voltage O I Digital output current sense Voltage range at Vsense, X2, PA_IN-, PA_IN+, CL X2,PA_IN- Inputs ...
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... PA_OUT pin Maximum output transmitting current in I(PA_OUT) programmable current limiting 8/44 Parameter Test Condition Maximum total current V < 4.75V with Digital supply provided externally R = 1.4kΩ (as in Figure Value 100 650 1.2 V -4.5 CC =1Ω LOAD 500 17) ST7540 Unit V/ms mArms mArms ...
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... ST7540 4 Electrical characteristics Table 5. Electrical characteristics ( V = +5V unless otherwise specified) Symbol V Digital supply voltages DD V Power supply voltage CC Digital input supply I current Power supply current current with digital I supply provided externally Under voltage lock out UVLO Threshold on V UVLO Hysteresis on UVLO ...
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... TX_OUT Fc = 86KHz, no load R = 0Ω CL Figure 17 pin sense Figure 17 ≤ 85°C, T < 125° Min. Typ. Max 0.75 GND + 0.4 Figure 4 5 Figure 4 2 1.75 2.3 3.5 1.7 2 0 160 180 200 ±18 ST7540 Unit MHz Ω pF mArms GST ...
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... ST7540 Table 5. Electrical characteristics (continued +5V unless otherwise specified) Symbol V V SENSE impedance Current control loop CL reference threshold pin Hysteresis on current CL loop reference HYST threshold T Carrier activation time RxTx Carrier stabilization time T from STEP 16 to zero ALC or from step 16 to step 31, ...
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... Carrier frequency: 86KHz Figure 5.6V PA_OUT V = 12V 30Ω LOAD Carrier frequency: 86KHz Figure 3 ≤ 85°C, T < 125° Min. Typ. Max - 0.5 2 250 100 140 0.5 2 250 V BU 83.5 86 ST7540 Unit rms µV rms dB/ µVrms V rms kΩ mV rms µV rms dB/ µVrms dB/ µVrms ...
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... ST7540 Table 5. Electrical characteristics (continued +5V unless otherwise specified) Symbol 5V Voltage regulator Linear regulator output VDC voltage 3.3V Voltage regulator Linear regulator output V DD voltage Other functions T Reset time RSTO T Watch-dog pulse width See WD Watch-dog pulse T WM period T Watch-dog time out time out ...
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... Figures 8, 9, 10, 11 & 12 see Figures 8, 9, 10, 11 & 12 see Figures 8, 9, 10, 11 & 12 100 pF Ω Vcc PA_IN - PA PA_IN + Vss ≤ 85°C, T < 125° Min. Typ. 1667 833 417 13) 208 1uF PA_OUT 30 Ω Measurement point ST7540 Max. Unit µ 2 D03IN1426 ...
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... ST7540 5 Crystal resonator and external clock Figure 4. External clock waveform Figure 5. Crystal Resonator Crystal resonator and external clock D03IN1425A 15/44 ...
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... Table 6. Channels List 1. Default value 6.2 Baud rates ST7540 is a multi Baud rate device: four Baud Rate are available (See Table 7. ST7540 mark and space tones frequency distance Vs. baud rate and deviation Baud Rate [Baud] 600 1200 (4) 2400 4800 1 ...
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... With Deviation = “0.5” the difference in terms of frequency between the mark and space tones is half the Baudrate value (∆F=0.5*BAudrate). When the Deviation = “1” the difference is the Baudrate itself (∆F= Baudrate). The minimal Frequency Deviation is 600Hz. Table 8. ST7540 synthesized frequencies Carrier Baud ...
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... Synchronous Mains access: on clock signal recovered by a PLL from ST7540 (CLR/T line) rising edge, value on FSK Demodulator is read and put to the data reception line (RxD line). ST7540 recovers the bit timing timing according to the BaudRate Selected. ● Asynchronous Mains access: Value on FSK Demodulator is sent directly to the data reception line (RxD line) ...
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... Data Reception by setting the idle state of RxD line. When ST7540 is in Receiving mode (REG_DATA=”0” and RxTx =“1”) and no data are available on mains (or RxD is forced to an idle state, i.e. with a conditioned Detection Method), the RxD line is forced to “ ...
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... Mode and control the Bit time in transmission mode. If RxTx line is set to “1” & REG_DATA=”0” (Data Reception), ST7540 enters in an Idle State. After Tcc time the modem starts providing received data on RxD line. ...
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... When ST7540 is in transmitting mode the clock reference is internally generated and TxD line is sampled on CLR/T rising Edge. If RxTx line is set to “1” & REG_DATA=”0” (Data Reception), ST7540 enters in an Idle State and CLR/T line is forced Low. After Tcc time the modem starts providing received data on RxD line. If RxTx line is set to “ ...
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... In Normal Control Register mode (Control Register bit 21 = ”0”, see 24 bits are transferred to ST7540 only latest 24 bits are stored inside the Control Register. If less than 24 bits are transferred to ST7540 the Control Register writing is aborted. In order to avoid undesired Control Register writings caused by REG_DATA line fluctuations (for example because of surge or burst on mains), in Extended Control Register mode (Control Register bit 21 = ” ...
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... Mark and Space Frequency in Receiving Mode must be distant at least BaudRate/2 to have a correct demodulation. While ST7540 is in Receiving Mode (RxTx pin =”1”), the transmit circuitry, Power Line Interface included, is turned off. This allows the device to achieve a very low current consumption (5mA typ). ...
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... Edges. The maximum number of transition required to reach the lock-in condition is 5. When in lock-in condition the PLL is sensitive only to RxD rising Edges to reduce the CLR/T Jitter. ST7540 PLL is forced in the un-lock condition, when more than 32 equal symbols are received.Due to the fact that the PLL, in lock-in condition, is sensitive only to RxD rising edge, sequences equal or longer than 15 equal symbols can put the PLL into the un-lock condition ...
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... ST7540 ● Carrier Detection The Carrier/Preamble detection Block notifies to the host controller the presence of a Carrier when it detects on the RX_IN Input a signal with an harmonic component close to the programmed Carrier Frequency. The CD_PD signal sensitivity is identical to the data reception sensitivity (0.5mVrms Typ. in Normal Sensitivity Mode). When the device sensitivity is set by the TxD line (Sensitivity level equal to BU threshold) the CD_PD signal is conditioned to the BU signal ...
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... FSK modulator. ● Synchronous Mains access: on CLR/T rising edge, TxD Line Value is read and sent to the FSK Modulator. ST7540 manages the Transmission timing according to the BaudRate Selected ● Asynchronous Mains access: TxD data enter directly to the FSK Modulator.The Host Controller manages the Transmission timing In both conditions no Protocol Bits are added by ST7540 ...
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... ST7540 In the analog domain, the signal is filtered in order to reduce the output signal spectrum and to reduce the harmonic distortion. The transition between a symbol and the following is done at the end of the on-going half FSK sinewave cycle. Figure 16. Transmitting path block diagram ● Automatic Level Control (ALC) The Automatic Level Control Block (ALC variable gain amplifier (with 32 non linear discrete steps) controlled by two analog feed backs acting at the same time ...
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... The next gain level is decreased by 1 step TH HYST PA_OUT/TX_OUT ALC Vsense VOLTAGE LOOP 10nF CL CURRENT LOOP RCL 80pF typ. AVss D03IN1421 ≅ ⋅ ( ------------------- - V Vsense OUTPK connected between CL and V No Gain Change HYST Vout R1 Vsense R2 Vsense ± ) Vsense TH HYST ST7540 . The SS HYST TH 1.865V (Typ HYST ...
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... ST7540 Table 11. V Vs. R1 & R2 resistors value OUT Vout (Vrms) 0.150 0.250 0.350 0.500 0.625 0.750 0.875 1.000 1.250 1.500 Note: Notes: The rate of R2 takes in account the input resistance on the V capacitor effect has been neglected. Figure 18. Typical output current vs RCL ...
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... Inputs and outputs of PA are available on pins PA_IN-,PA_IN+ and PA_OUT. User can easily select an appropriate active filtering topology to filter the signal present on TX_OUT pin. TX_OUT output has a current capability much lower than PA_OUT. 30/44 relationship CC cc ≤ PA_OUT(AC) ≤ 1.5V ss ST7540 V PA_OUT(DC) t D03IN1425 ...
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... ST7540 Figure 20. Power line interface topology Figure 21. Power line interface startup timing diagram TX_OUT Vcc PA_IN- - PA_OUT + PA_IN+ TX_OUT ALC Vss Vsense VOLTAGE LOOP CL CURRENT LOOP RCL 80pF typ. D03IN1422 RxTx T T RXTX ST 2.1V 0V STEP NUMBER 16 Functional description ALC D03IN1408 AC LINE ...
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... Functional description 6.8 Control register The ST7540 is a multi-channel and multifunction transceiver. An internal Bits (in Extended mode) Control Register allows to manage all the programmable parameters (Table 12). The programmable functions are: ● Channel Frequency ● Baud Rate ● Deviation ● Watchdog ● Transmission Timeout ● ...
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... ST7540 Table 12. Control register functions Function Frequencies 82.05 KHz 110 KHz 132.5 KHz Baud rate 5 Deviation 6 Watchdog Disabled Enabled (1.5 s) Disabled Transmission time out Not Used Frequency detection time 11 Reserved Value Selection Bit2 Bit1 Bit0 60 KHz KHz KHz KHz KHz Bit 4 ...
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... Active only if extended control register is enable (Bit 21=”1”) Active only if extended control register is enable (Bit 21=”1”) Active only if header recognition function (Bit 18=”1”) and extended control register (Bit 21=”1”) are enable ST7540 Default Carrier detection without conditioning 4 MHz Disabled Disabled ...
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... ST7540 Table 12. Control register functions Function Header 20 Length Extended Disable (24 bits) 21 Register Enabled (48 bits) Sensitivity Normal Sensitivity 22 Mode High Sensitivity Disabled 23 Input Filter Enabled Frame from 0000h Header Frame Length from 01h to FFh Value Selection Bit 20 8 bits 0 16 bits 1 Bit 21 ...
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... During the time out period only register access or reception mode are enabled. During Reset sequence if RxTx line =”0” & REG_DATA line =”0”, Time Out protection is suddenly enabled and ST7540 must be configured in data reception after the reset event before starting a new data transmission. ...
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... RSTO Output is a reset generator for the application circuitry. During the ST7540 startup sequence is forced low. RSTO becomes high after a T startup sequence. Inside ST7540 is also embedded a watchdog function. The watchdog function is used to detect the occurrence of a software fault of the Host Controller. The watchdog circuitry generates an internal and external reset (RSTO low for T watchdog timer ...
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... Thermal shutdown The ST7540 is provided of a thermal protection which turn off the PLI when the junction temperature exceeds 170°C ±10% . Hysteresis is around 30°C. When shutdown threshold is overcome, PLI interface is switched OFF. Thermal Shutdown event is notified to the HOST controller using BU/THERM line. When BU/THERM line is High, ST7540 junction temperature exceed the shutdown threshold (Not Latched) ...
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... ST7540 Figure 24. Power-up sequence Voltage 5V/3. Auxiliary analog and digital functions Time D03IN1424 39/44 ...
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... Auxiliary analog and digital functions Figure 25. Application schematic example with coupling transformer. 40/44 ST7540 ...
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... ST7540 8 Mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... ST7540 inch Typ. Max. 0.047 0.006 0.039 0.041 0.012 0.008 0.382 0.385 0.252 0.260 0.173 0.177 0.026 0.024 0.029 ...
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... ST7540 9 Revision history Table 14. Revision history Date 15-Mar-2006 25-Sep-2006 Revision 1 Initial release. 2 Updated Electrical Characteristics and Power Amplifier description Revision history Changes 43/44 ...
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... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 44/44 Please Read Carefully: © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com ST7540 ...