SI5040-A-GM Silicon Laboratories Inc, SI5040-A-GM Datasheet - Page 22
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SI5040-A-GM
Manufacturer Part Number
SI5040-A-GM
Description
IC TXRX XFP 10GBPS 32MLP
Manufacturer
Silicon Laboratories Inc
Type
Transceiverr
Specifications of SI5040-A-GM
Voltage - Supply
1.8V, 3.3V
Mounting Type
Surface Mount
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Product
RF / Wireless
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Protocol
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Si5040
5.5. Receiver Slice Control
In order to optimize the bit error rate performance of the
system, the receiver supports automatic and manual
adjustment of the 0/1 decision threshold (slice control).
Four slice modes can be programmed via Register 20
as detailed below:
22
AutoSlice Mode (sliceEn[2:0] = 001): The slice is
automatically set without any control by the user. An
internal estimate of the eye opening is used to
automatically adjust the slice voltage. This mode can
be used when there is no FEC processor as it
continually adjusts the slice voltage. Registers 22/21
have no effect on this mode of operation.
Constant Duty Cycle Mode (sliceEn[2:0] = 010):
This mode continually adjusts the slice voltage to
maintain a user-selected duty cycle at the limiting
amplifier output. The duty cycle can be set in the
sliceLVL register (Registers 22 and 21). This mode
can be used when there is no FEC processor,
however, if the duty cycle is dynamically controlled
the recommended duty cycle step size is less than or
equal to 0.1%. In an actual system the duty cycle
should not be set to less than 45% or greater than
55%. For the case of maximum dispersion, an
optimally-set duty cycle will typically perform slightly
better than Autoslice.
Proportional Mode (sliceEn[2:0] = 011):The slice
offset is defined as a percentage of the peak-to-peak
value of the input signal. The percent value is written
in the sliceLVL register (Registers 22 and 21) as an
offset from 50%. Due to drifts and temperature
variations in the silicon, the slice offset values must
be dynamically modified at a rate of 100 ms or faster.
This mode is recommended only when a FEC
processor is present to control the slice level.
VCOCAL[1:0] = 01?
Figure 14. Receive and Transmit CDR and VCO Behaviors Upon Declaring LOL
Y
The entire VCO
frequency range will be
swiped to start the CDR
lock acquisition process.
VCOCAL[1:0] = 00?
present?
Is refClk
N
Y
Y
The internal VCO pull
range will be automatically
re-centered to the
reference clock frequency
to start the CDR lock
acquisition process.
LOL=1?
Rev. 0.86
Autoslice and constant duty cycle are the preferred slice
modes of operation for Telecom and Datacom
applications.
5.6. Clock and Data Recovery (CDR)
The Si5040 integrates a CDR to recover the clock and
data from the input signal applied to RXDIN. The CDR
can be operated with or without an external reference
clock.
programmed in the RxCalConfig register (Register 8). If
a reference clock is applied to the receiver, the CDR
can be forced to lock to the reference clock in the event
that a loss of signal occurs. The CDR can be
programmed to continue to sample the RXDIN input
while the receive PLL is locked to the reference clock.
These options are controlled in the RxConfig register
(Register 7).
5.7. Reference Clock
The Si5040 will operate with or without an external
reference clock. If a reference clock is applied, the
receiver uses the reference clock to center the internal
VCO pull range, which, in turn, reduces the acquisition
time of the CDR. If the reference clock is not applied,
the entire VCO frequency range will be swept for lock
acquisition.
Note that since the applied reference clock is used for
both the receiver and the transmitter and since the
Y
Absolute Mode (sliceEn[2:0] = 100): The slice offset
is defined as an absolute voltage. The offset can be
set in the range of –240 to +240 mV in the sliceLVL
register (Registers 22 and 21). Just as in
proportional mode, the slice offset values must be
dynamically modified at a rate of 100ms or faster.
This mode is recommended only when a FEC
processor is present to control the slice level.
Reference
Y
VCO stays at the center
of its frequency range
awaiting for refClk
VCOCAL[1:0] = 10
Is refClk present?
(Default)?
or
N
Y
referenceless
VCOCAL[1:0] = 11?
LOL will stay on.
Invalid mode!
operation
Y
is