Z16FMC64AG20EG Zilog, Z16FMC64AG20EG Datasheet - Page 183
![Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D](/photos/39/69/396954/tqfp-64_sml.jpg)
Z16FMC64AG20EG
Manufacturer Part Number
Z16FMC64AG20EG
Description
Microcontrollers (MCU) 16BIT 64K FL 4K RAM 2UART 12CH 10BIT A/D
Manufacturer
Zilog
Series
Z16FMCr
Datasheet
1.Z16FMC28AG20_EG.pdf
(341 pages)
Specifications of Z16FMC64AG20EG
Processor Series
Z16FMC
Core
ZNEO
Data Bus Width
16 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
4 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
LQFP-64
Development Tools By Supplier
Z16FMC28200KITG
Minimum Operating Temperature
- 40 C
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Eeprom Size
-
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16FMC64AG20EG
Manufacturer:
Zilog
Quantity:
160
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ESPI Control Register Definitions
PS028702-1210
ESPI Data Register
SPI BRG Interrupt Interval (s)
Minimum baud rate is obtained by setting BRG[15:0] to 0000H for a clock divisor value
of (2 x 65536 = 131072).
When the ESPI is disabled, the BRG functions as a basic 16-bit timer with interrupt on
timeout. Observe the following steps to configure the BRG as a timer with interrupt on
timeout:
1. Disable the ESPI by clearing the ESPIEN1,0 bits in the ESPI Control Register.
2. Load the appropriate 16-bit count value into the ESPI Baud Rate High and Low Byte
3. Enable the BRG timer function and associated interrupt by setting the BRGCTL bit in
When configured as a general purpose timer, the SPI BRG interrupt interval is calculated
using the following equation:
The remainder of this chapter describes the functions of the following ESPI control regis-
ters.
•
•
•
•
•
•
•
The ESPI Data Register (see Table 89) addresses both the outgoing Transmit Data Regis-
ter and the incoming Receive Data Register. Reads from the ESPI Data Register return the
contents of the Receive Data Register. The Receive Data Register is updated with the con-
SPI Baud Rate (bps)
registers.
the ESPI Control Register to 1.
ESPI Data Register
ESPI Transmit Data Command Register
ESPI Control Register
ESPI Mode Register
ESPI Status Register
ESPI State Register
ESPI Baud Rate High and Low Byte Registers
=
P R E L I M I N A R Y
System Clock Frequency (Hz)
--------------------------------------------------------------------------- -
2 BRG[15:0]
=
System Clock Period (s) BRG[15:0]
Z16FMC Series Motor Control MCUs
Enhanced Serial Peripheral Interface
Product Specification
161
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