AD1895AYRSZ Analog Devices Inc, AD1895AYRSZ Datasheet
AD1895AYRSZ
Specifications of AD1895AYRSZ
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AD1895AYRSZ Summary of contents
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FEATURES Automatically Senses Sample Frequencies No Programming Required Attenuates Sample Clock Jitter 3 Input and 3.3 V Core Supply Voltages Accepts 16-/18-/20-/24-Bit Data Up to 192 kHz Sample Rate Input/Output Sample Ratios from 7.75:1 to ...
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AD1895–SPECIFICATIONS TEST CONDITIONS, UNLESS OTHERWISE NOTED. Supply Voltages VDD_CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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DIGITAL TIMING (–40 C < T < +105 C, VDD_CORE = 3 Parameter t MCLK_IN Period MCLKI f MCLK_IN Frequency MCLK t MCLK_IN Pulsewidth High MPWH t MCLK_IN Pulsewidth Low MPWL INPUT SERIAL PORT TIMING t LRCLK_I ...
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AD1895 –SPECIFICATIONS DIGITAL FILTERS (VDD_CORE = 3.3 V Parameter Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Specifications subject to change without notice. DIGITAL I/O CHARACTERISTICS (VDD_CORE = 3.3 V Parameter Input Voltage High (V ) ...
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POWER SUPPLIES (VDD_CORE = 3.3 V Parameter TOTAL ACTIVE POWER DISSIPATION 48 kHz: 48 kHz 96 kHz: 96 kHz 192 kHz: 192 kHz TOTAL POWER-DOWN DISSIPATION (RESET LOW) Specifications subject to change without notice. TEMPERATURE RANGE Parameter Specifications Guaranteed Functionality ...
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AD1895 Pin No. IN/OUT (I/O) Mnemonic MCLK_IN 3 OUT MCLK_OUT 4 IN SDATA_I 5 IN/OUT SCLK_I 6 IN/OUT LRCLK_I 7 IN VDD_IO 8 IN DGND 9 IN BYPASS 10 IN SMODE_IN_0 11 IN SMODE_IN_1 12 ...
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FREQUENCY – kHz TPC 1. Wideband FFT Plot (16 k Points) 0 dBFS 1 kHz Tone, 48 kHz: 48 kHz (Asynchronous) 0 –20 ...
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AD1895 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 0 2.5 5.0 7.5 10.0 12.5 FREQUENCY – kHz TPC 7. Wideband FFT Plot (16 k Points) 192 kHz: 48 kHz, 0 dBFS 1 kHz Tone –50 –60 ...
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FREQUENCY – kHz TPC 13. Wideband FFT Plot (16 k Points) 96 kHz: 48 kHz, –60 dBFS ...
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AD1895 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 FREQUENCY – kHz TPC 19. Wideband FFT Plot (16 k Points) 192 kHz: 192 kHz, 0 dBFS 80 kHz Tone 0 –20 ...
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OUTPUT SAMPLE RATE – Hz TPC 25. THD + N vs. Output Sample Rate dBFS 1 kHz Tone –119 –121 –123 –125 ...
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AD1895 –119 –121 –123 –125 –127 –129 –131 –133 –135 30000 66000 102000 48000 84000 120000 OUTPUT SAMPLE RATE – Hz TPC 31. DNR (Unweighted) vs. Output Sample Rate kHz, –60 dBFS 1 kHz Tone S_IN 0 ...
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INPUT LEVEL – dBFS TPC 37. Linearity Error, 48 kHz: 44.1 kHz, 0 dBFS to –140 dBFS Input, 200 Hz Tone ...
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AD1895 –110.0 –112.5 –115.0 –117.5 –120.0 –122.5 –125.0 –127.5 –130.0 –132.5 –135.0 –137.5 –140.0 –140 –120 –100 –80 –60 INPUT LEVEL – dBFS TPC 43. THD + N vs. Input Amplitude, 48 kHz: 44.1 kHz, 1 kHz Tone –110.0 –112.5 ...
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FREQUENCY – kHz TPC 49. THD + N vs. Frequency Input, 48 kHz: 44.1 kHz, 0 dBFS –110 –120 –130 –140 –150 –160 –170 –180 2.5 5.0 ...
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AD1895 ASRC FUNCTIONAL OVERVIEW THEORY OF OPERATION Asynchronous sample rate conversion is converting data from one clock source at some sample rate to another clock source at the same or different sample rate. The simplest approach to asyn- chronous sample ...
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IN INTERPOLATE LOW-PASS BY N FILTER f S_IN f FREQUENCY DOMAIN OF SAMPLES AT FREQUENCY DOMAIN OF THE INTERPOLATION SIN(X)/X OF ZERO-ORDER HOLD f FREQUENCY DOMAIN OF RESAMPLING S_OUT FREQUENCY DOMAIN AFTER RESAMPLING Figure 6. Frequency Domain of the Interpolation ...
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AD1895 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 –190 –200 –210 –220 0.01 0.1 Figure 8. Frequency Response of the Digital Servo Loop. f frequency is 30 ...
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OPERATING FEATURES RESET and Power-Down When RESET is asserted low, the AD1895 will turn off the master clock input to the AD1895, MCLK_IN, initialize all of its internal registers to their default values, and three-state all of the I/O pins. ...
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AD1895 Serial Data Ports—Data Format The Serial Data Input Port Mode is set by the logic levels on the SMODE_IN_0/SMODE_IN_1/SMODE_IN_2 pins. The serial data input port modes available are left justified, I justified (RJ), 16, 18, 20 bits, ...
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TDM MODE APPLICATION In TDM Mode, several AD1895s can be daisy-chained together and connected to the serial input port of a SHARC AD1895 contains a 64-bit parallel load shift register. When the LRCLK_O pulse arrives, each AD1895 parallel loads its ...
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AD1895 Serial Data Port Master Clock Modes Either of the AD1895 serial ports can be configured as a master serial data port. However, only one serial port can be a master, while the other has slave. In ...
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PIN 1 2.00 MAX 0.05 MIN REV. B OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9. 5.60 8.20 5.30 7.80 5.00 7. 1.85 1.75 0.10 1.65 COPLANARITY 0.25 ...
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AD1895 Revision History Location 9/02—Data Sheet changed from REV REV. B. Changes to SPECIFICATIONS (Digital Performance ...