Z8623012SSG Zilog, Z8623012SSG Datasheet - Page 18

• Manufacturer Part Number: Z8623012SSG
• Description: IC SMART V-CHIP W/2ND I2C 18SOIC
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8623012SSG

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 18-SOIC (7.5mm Width)
• Processor Series: Z8623x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: CMOS
• Maximum Clock Frequency: 12 MHz
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Details

4.
4.1 I
4.1.1 The I
4.1.2 Bus Conditions
18
SERIAL COMMUNICATIONS INTERFACE
2
C B
2
C Bus Protocol
US
S
O
ERIAL
PERATION
C
Commands and data are sent to and from the Z86230 through its I
munications interface. This port is the path for setting the configuration and oper-
ational modes of the device. The interface is also used as the port for outputting
the recovered XDS data.
The Z86230 supports a bidirectional 2-wire bus and data transmission protocol.
The bus is controlled by the master device, which generates the serial clock
(
The serial data (
device with two possible slave addresses. When the
address is
the slave address is
The Z86230 can receive or transmit data under control of the master device. Com-
munication is initiated when the master device sends the
lowed by the Z86230 Slave Address
The Z86230 responds with an Acknowledge.
The
below in Table 4.
T
The Bus Protocol requires that:
1. Data transfer can only be started when the bus is not busy.
2. During data transfer, data transitions must not occur while the clock is High.
Bus Conditions are defined as:
Not Busy.
START.
STOP.
1
2
N
2
OMMUNICATIONS
SCLK
ABLE
st
nd
nd
OTE
I
I
2
I
I
2
2
2
:
C Address
C RD
C Address
C Address.
Low(0) on pin 1 selects the 1
), controls the bus access, and generates the
4. Z86230 I
A Low-to-High transition of the
A High-to-Low transition of the
28h
Data and Clock lines are both High.
/
WR
Z86230—PRELIMINARY
SDA
for
bit is the Least Significant Bit (LSB) of the I
I
NTERFACE
2
C S
WRITE
2Ah
) pin is the bidirectional data line. The Z86230 is a slave
LAVE
for
and
A
WRITE
DDRESSES
29h
st
READ
and
READ
I
for
2
29h
2Bh
C Address; HIGH(1) on pin 1 selects the
SDA
SDA
READ
2Bh
byte or Slave Address
line while the
line while the
for
. When the
START
READ
I
2
C SEL
START
.
and
I
SCLK
2
pin is Low, the slave
2
SCLK
PS000401-TVC0699
C SEL
C addresses listed
STOP
I
WRITE
2
condition fol-
C B
WRITE
2
line is High.
28h
2Ah
C serial com-
line is High.
pin is High,
US
conditions.
O
PERATION
byte.