Z8622912PSG Zilog, Z8622912PSG Datasheet - Page 9

• Manufacturer Part Number: Z8622912PSG
• Description: IC CCD W/2ND I2C ADD 18-DIP
• Manufacturer: Zilog
• Type: Video Decoderr

Specifications of Z8622912PSG

• Applications: Set-Top Boxes, TV
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Mounting Type: Through Hole
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: Z8622x
• Core: Z80
• Data Bus Width: 8 bit
• Program Memory Type: CGROM
• Program Memory Size: 3.7 B
• Maximum Clock Frequency: 12 MHz
• Operating Supply Voltage: 4.75 V to 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply, Analog: -
• Lead Free Status / Rohs Status: Details

ZiLOG
Z86229 BLOCK DIAGRAM DESCRIPTION
The Z86229 is designed to process both fields of Line 21
on a television VBI and provide the functional performance
of a Line 21 Closed-Caption decoder and Extended Data
Service decoder. This device requires two input signals,
Composite Video and a horizontal timing signal (HIN), and
several passive components for proper operation. A vertical
input signal is also required if OSD display mode is required
when no video signal is present. The Decoder performs sev-
eral functions, including extraction of data from Line 21,
separation of the normal Line 21 data from the XDS data,
on-screen display of the selected data channel, and output-
ting of the XDS data through the serial communications
channel.
Input Signals
The Composite Video input signal is rated at a nominal 1.0
Volt p-p, with sync tips negative and band-limited to
600 kHz. The Z86229 operates with an input level variation
of ±3 dB.
The HIN input signal is necessary to bring the VCO close
to the required operating frequency. This signal must be a
CMOS-level signal. The HIN signal can have positive or
negative polarity, and the signal is only required to be within
3% of the standard H frequency. When configured for EXT
HLK operation, this signal should correspond to the H Fly-
back signal.
The timing difference between the HIN rising edge and the
leading edge of composite sync (of VIDEO input) is one of
the factors that affects the horizontal position of the display.
Any shift resulting from the timing of this signal can be com-
pensated for with the horizontal timing value in the H Po-
sition register.
Video Input Signal Processing
The Composite Video input is AC-coupled to the device.
The sync tip is internally clamped to a fixed reference volt-
age by means of a dual clamp. Initially, the unlocked signal
is clamped using a simple clamp. Improved impulse noise
performance is then achieved after the internal sync circuits
lock to the incoming signal. Noise rejection is obtained by
making the clamp operative only during the sync tip. The
clamped composite video signal is fed to both the Data Slic-
er and Sync Slicer blocks.
The Data Slicer generates a clean CMOS-level data signal
by slicing the signal at its midpoint. The slice level is es-
tablished on an adaptive basis during Line 21. The resulting
value is stored until the next occurrence of Line 21. A high
level of noise immunity is achieved by using this process.
The Sync Slicer processes the clamped Comp Video signal
to extract Comp Sync. This signal is used to lock the inter-
nally generated sync to the incoming video when the video-
lock mode of operation has been enabled. Sync slicing is
performed in two steps. In the non-locked mode, the sync
is sliced at a fixed offset level from the sync tip. When prop-
er lock operation has been achieved, the slice level voltage
switches from a fixed reference level to an adaptive level.
The slice level is stored on the sync slice capacitor
(CSYNC).
The Data Clock Recovery circuit operates in conjunction
with the Digital H-lock circuit. The circuit produces a 32H
clock signal (DCLK) that is locked in phase to the clock run-
in burst portion of the sliced data obtained from the Data
Slicer. When the Line 21 code appears, the DCLK phase
lock is achieved during the clock run-in burst and is used
to reclock the sliced data. After phase lock is established it
is maintained until a change in the video signal occurs.
The Digital H-Lock circuit produces a variety of signals, in-
cluding the video timing gates, PG and STG. These signals
are all locked in-phase with the HSYNC and the video tim-
ing signal, no matter which H-lock mode is used in the dis-
play generation circuits. This independent phase lock loop
is able to respond quickly to changes in video timing without
concern for display stability requirements.
VCO and One Shot
All internal timing and synchronizing signals are derived
from the on-board 12-MHz VCO. The VCO output is the
DOT CLK signal used to drive both the Horizontal and Ver-
tical counter chains and display timing. The One Shot circuit
produces a horizontal timing signal which is derived from
the incoming video, and qualified by a Copy Guard logic
circuit.
The VCO can be locked in phase to two different sources.
For television operation, where a good horizontal display
timing signal is available, the VCO is locked to the HIN in-
put through the action of the Phase Detector (PH2). When
a proper HIN signal is not available (such as in a VCR), the
VCO can be locked to the incoming video through the Phase
Detector (PH1). In this case, the frequency detector (FR)
circuit is activated (as required) to bring the VCO within
the pull-in range of PH1.
Timing and Counting Circuits
The DOT CLK is first divided down to produce the char-
acter timing clock CHAR CLK. This signal is then further
divided to generate the horizontal timing signals H, 2H and