MAX7403ESA+ Maxim Integrated Products, MAX7403ESA+ Datasheet - Page 10

• Manufacturer Part Number: MAX7403ESA+
• Description: IC FILTER LOWPASS 8-SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX7403ESA+

• Filter Type: Elliptic, Lowpass Switched Capacitor
• Frequency - Cutoff Or Center: 10kHz
• Number Of Filters: 1
• Max-order: 8th
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Number Of Channels: Single
• Cutoff Frequency: 10 KHz
• Supply Voltage (max): 5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 5 V
• Supply Voltage (min): 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX7400/MAX7403/MAX7404/MAX7407 SCFs
were designed for use with external clocks that have a
40% to 60% duty cycle. When using an external clock,
drive CLK with a CMOS gate powered from 0 to V
Varying the rate of the external clock adjusts the filter
corner frequency:
When using the internal oscillator, the capacitance
(C
quency:
where K = 38 for the MAX7400/MAX7403, and K = 34
for the MAX7404/MAX7407. Since the capacitor value
is in picofarads, minimize the stray capacitance at CLK
so that it does not affect the internal oscillator frequen-
cy. Varying the rate of the internal oscillator adjusts the
filter’s corner frequency by a 100:1 clock-to-corner fre-
quency ratio. For example, an internal oscillator fre-
quency of 100kHz produces a nominal corner
frequency of 1kHz.
The MAX7400/MAX7403/MAX7404/MAX7407’s input
impedance is effectively that of a switched-capacitor
resistor and is inversely proportional to frequency. The
8th-Order, Lowpass, Elliptic,
Switched-Capacitor Filters
Figure 3. Elliptic Filter Response
10
OSC
______________________________________________________________________________________
) on the CLK pin determines the oscillator fre-
f
OSC
PASSBAND
(kHz) =
f
f
C
C
= f
K
f
C
C
CLK
OSC
vs. Clock Frequencies
10
f
S
TRANSITION RATIO =
/ 100
3
RIPPLE
f
S
; C
Input Impedance
OSC
STOPBAND
FREQUENCY
Clock Signal
External Clock
Internal Clock
in pF
f
f
S
C
DD
.
input impedance determined by the following equation
represents the average input impedance, since the
input current is not continuous. As a rule, use a driver
with an output source impedance less than 10% of the
filter’s input impedance. Estimate the input impedance
of the filter using the following formula:
where f
These devices feature a shutdown mode that is activat-
ed by driving SHDN low. Placing the filter in shutdown
mode reduces the supply current to 0.2µA (typ) and
places the output of the filter into a high-impedance
state. For normal operation, drive SHDN high or con-
nect to V
The voltage at COM sets the common-mode input volt-
age and is internally biased at midsupply by a resistor-
divider. Bypass COM with a 0.1µF capacitor and
connect OS to COM. For applications requiring offset
adjustment or DC level shifting, apply an external bias
voltage through a resistor-divider network to OS, as
shown in Figure 4. (Note: Do not leave OS unconnect-
ed.) The output voltage is represented by the following
equation:
Figure 4. Offset Adjustment Circuit
0.1 F
CLOCK
INPUT
CLK
V
DD
SUPPLY
= clock frequency and C
.
V
OUT
Z
Applications Information
IN
CLK
IN
( )
Low-Power Shutdown Mode
= (V
Offset and Common-Mode
MAX7400
MAX7403
MAX7404
MAX7407
V
IN
GND
DD
(
- V
f
CLK
COM
SHDN
COM
OUT
1
OS
Input Adjustment
) + V
C
IN
0.1 F
0.1 F
IN
= 0.85pF.
)
OS
OUTPUT
50k
50k
50k