MCP23S08-E/SS Microchip Technology, MCP23S08-E/SS Datasheet - Page 15

• Manufacturer Part Number: MCP23S08-E/SS
• Description: IC I/O EXPANDER SPI 8B 20SSOP
• Manufacturer: Microchip Technology

Specifications of MCP23S08-E/SS

• Package / Case: 20-SSOP
• Interface: SPI
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 10MHz
• Voltage - Supply: 1.8 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Includes: POR
• Logic Family: MCP23S08
• Propagation Delay Time: 50 ns
• Operating Supply Voltage: 1.8 V to 5.5 V
• Power Dissipation: 700 mW
• Operating Temperature Range: - 40 C to + 125 C
• Input Voltage: 1.8 V to 5.5 V
• Logic Type: I/O Expander
• Maximum Clock Frequency: 10 MHz
• Maximum Operating Frequency: 1.7 MHz
• Mounting Style: SMD/SMT
• Output Current: 25 mA
• Output Voltage: 1.8 V to 4.5 V
• Chip Configuration: 8 Bit
• Bus Frequency: 10MHz
• Ic Interface Type: Serial, SPI
• No. Of I/o's: 8
• Supply Voltage Range: 1.8V To 5.5V
• Digital Ic Case Style: SSOP
• No. Of Pins: 20
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Delay Time: 50ns
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: GPIODM-KPLCD - BOARD DEMO LCD GPIO EXP KEYPAD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.6.8
The INTF register reflects the interrupt condition on the
port pins of any pin that is enabled for interrupts via the
GPINTEN register. A ‘set’ bit indicates that the
associated pin caused the interrupt.
This register is ‘read-only’. Writes to this register will be
ignored.
REGISTER 1-8:
© 2005 Microchip Technology Inc.
bit 7-0
INTERRUPT FLAG (INTF)
REGISTER
INTF – INTERRUPT FLAG REGISTER (ADDR 0x07)
INT7:INT0: These bits reflect the interrupt condition on the port. Will reflect the change only if
interrupts are enabled (GPINTEN) <7:0>.
1 = Pin caused interrupt.
0 = Interrupt not pending.
Legend:
R = Readable bit
- n = Value at POR
bit 7
INT7
R-0
INT6
R-0
INT5
R-0
W = Writable bit
‘1’ = Bit is set
MCP23008/MCP23S08
INT4
R-0
Note:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
INT3
R-0
INTF will always reflect the pin(s) that
have an interrupt condition. For example,
one pin causes an interrupt to occur and is
captured in INTCAP and INF. If, before
clearing the interrupt, another pin changes
which would normally cause an interrupt, it
will be reflected in INTF, but not INTCAP.
INT2
R-0
x = Bit is unknown
INT1
R-0
DS21919B-page 15
INT0
R-0
bit 0