SX1505I087TRT Semtech, SX1505I087TRT Datasheet
SX1505I087TRT
Specifications of SX1505I087TRT
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SX1505I087TRT Summary of contents
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... The SX1504, SX1505 and SX1506 each come in a small QFN-UT-20/28 package as well as a TSSOP- 20/28 package. All devices are rated from -40° +85° C temperature range RDERING NFORMATION Part Number I/O Channels SX1504I087TRT 4 SX1505I087TRT 8 SX1506I091TRT 16 (1) SX1504I088TRT 4 (1) SX1505I088TRT 8 (1) SX1506I089TRT 16 ...
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... NFORMATION 6.1 Typical Application Circuit 6.2 Typical LED Operation 6.2.1 LED ON/OFF Control 6.2.2 LED Intensity Control 6.3 Keypad Implementation 6.4 Level Shifter Implementation Hints ACKAGING NFORMATION th Rev 2 – 30 August 2010 Table of Contents ............................................................................................... 7 ............................................................................... 10 ............................................................................................. 12 .................................................................................................. 19 ................................................................................................... 26 ..................................................................................................... 28 2 SX1504/SX1505/SX1506 4/8/16 Channel GPIO www.semtech.com ...
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... QFN-UT 28-pin Outline Drawing 7.4 QFN-UT 28-pin Land Pattern 7.5 TSSOP 20-pin Outline Drawing 7.6 TSSOP 20-pin Land Pattern 7.7 TSSOP 28-pin Outline Drawing 7.8 TSSOP 28-pin Land Pattern .............................................................................................................. 32 OLDERING ROFILE th Rev 2 – 30 August 2010 SX1504/SX1505/SX1506 4/8/16 Channel GPIO www.semtech.com ...
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... Leave open, not connected - Connect to VCC1 P Ground Pin - Leave open, not connected - Leave open, not connected 2 C interface Table 1 – SX1504 Pin Description SDA NC1 SCL GND (PAD) I/O[0] Figure 1 – SX1504 QFN-UT-20 Pinout 4 SX1504/SX1505/SX1506 4/8/16 Channel GPIO NC3 VDDM NC2 ADDR NINT www.semtech.com ...
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... DIO I/O[6], at power-on configured as an input (*1) DIO I/O[7], at power-on configured as an input 2 C interface Table 2 – SX1505 Pin Description SDA NC1 SCL GND (PAD) I/O[0] Figure 2 – SX1505 QFN-UT-20 Pinout 5 SX1504/SX1505/SX1506 4/8/16 Channel GPIO I/O[4] VDDM NC2 ADDR NINT www.semtech.com ...
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... DIO I/O[1], at power-on configured as an input 2 C interface Table 3 – SX1506 Pin Description 1 GND 2 I/O[2] TOP VIEW 3 I/O[3] GND VCC1 4 (PAD) I/O[4] 5 I/O[5] 6 GND 7 Figure 3 – SX1506 QFN-UT-28 Pinout 6 SX1504/SX1505/SX1506 4/8/16 Channel GPIO 21 GND 20 I/O[13] I/O[12] 19 VCC2 18 I/O[11] 17 I/O[10] 16 GND 15 www.semtech.com ...
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... V - 200 V -40 +85 ° C -40 +125 ° C -55 +150 ° C +/-100 - mA Min Typ Max Unit 2.5 - 5.5 2 µ µA 0.7* VCC1,2 - VCC1,2 +0.3 0.3* -0.4 - VCC1,2 0. VCC1,2 -1.5 - 1.5 µ VCC1,2 - VCC1,2 V – 0.3 -0 1.5 µ 0 www.semtech.com = µs µs ...
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... VDDM - VDDM +0.3 0.3* -0.4 - VDDM 0. VDDM -1 specification version 2 0 0.7* - 5.5 VDDM 0.3* -0.4 - VDDM 0 - 400 (3) ( 0.9 (5) 100 - - (6) 20+0.1C - 300 b (6) 20+0.1C - 300 b 0 www.semtech.com µ µ kHz µs µs µs µs µ µs ...
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... C-bus system, but the requirement t Table 5 – Electrical Specifications 9 SX1504/SX1505/SX1506 4/8/16 Channel GPIO Min Typ Max Unit 1 400 0.1*VDDM - - 0.2*VDDM - - - bridge the undefined region of MR min ) of the SCL signal. LOW 250 ns must then be met. SU;DAT + t = 1000 + 250 r max SU;DAT www.semtech.com µ ...
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... IDDM (uA) 1 3.2 VOL vs. IOL 0.15 0.1 VOL (V) 0. Doesn’t vary significantly with temperature th Rev 2 – 30 August 2010 IDDM vs VDDM VDDM (V) VOL vs IOL (VCC1,2=5.5V, High Sink IOs IOL (mA) 10 SX1504/SX1505/SX1506 4/8/16 Channel GPIO 90°C -40° Tamb 25 30 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING 3.3 VOH vs. IOH 5.5 5.4 5.3 VOH (V) 5.2 5 Doesn’t vary significantly with temperature th Rev 2 – 30 August 2010 SX1504/SX1505/SX1506 VOH vs IOH (VCC1,2=5.5V) 10 IOH (mA) 11 4/8/16 Channel GPIO * Tamb 20 www.semtech.com ...
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... I C Bus Control R/W SX1505 GND Figure 5 – SX1505 Block Diagram 12 SX1504/SX1505/SX1506 4/8/16 Channel GPIO VCC1 I/O[0] I/O Bank A I/O[1] A I/O[2] I/O[3] NINT Interrupt VCC1 I/O[0] I/O Bank A I/O[1] A I/O[2] I/O[3] VCC2 I/O[4] I/O Bank B I/O[5] A I/O[6] I/O[7] NINT Interrupt www.semtech.com ...
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... R/W SX1506 GND Figure 6 – SX1506 Block Diagram Undefined t PULSE 13 SX1504/SX1505/SX1506 4/8/16 Channel GPIO VCC1 I/O[0] I/O[1] I/O[2] I/O Bank A I/O[3] A I/O[4] I/O[5] I/O[6] I/O[7] VCC2 I/O[8] I/O[9] I/O[10] I/O Bank B I/O[11] A I/O[12] I/O[13] I/O[14] I/O[15] NINT Interrupt Undefined t RESET www.semtech.com ...
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... C devices and comply with the Philips interface has been designed for program flexibility, in that once 2 C logic, a tight software loop can be designed then acknowledges that it is being addressed, and the master Slave Address: 7 bit Register Address: 8 bit Data: 8 bit 14 SX1504/SX1505/SX1506 4/8/16 Channel GPIO 2 C www.semtech.com ...
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... The slave acknowledges this request and returns the data from the register location that had previously been set up. th Rev 2 – 30 August 2010 Figure 9 – Write RegData Register Slave Address: 7 bit Register Address: 8 bit Data: 8 bit 15 SX1504/SX1505/SX1506 4/8/16 Channel GPIO 2 C then www.semtech.com ...
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... Rev 2 – 30 August 2010 Slave Address: 7 bit Register Address: 8 bit Data: 8 bit SX1504 I/Os 1 GPIO GPIO 01 GPIO PLD OUT PLD IN 10 PLD OUT PLD IN PLD IN Table 7 – SX1504 PLD Modes Settings 16 SX1504/SX1505/SX1506 4/8/16 Channel GPIO 1 0 GPIO GPIO PLD IN PLD IN www.semtech.com ...
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... GPIO GPIO GPIO PLD OUT PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN GPIO GPIO GPIO PLD OUT PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN GPIO GPIO GPIO PLD OUT PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN www.semtech.com ...
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... What we need corresponds to the second line of the SX1505 PLD Table => RegPLDMode = “xx00xx01” 2. Fill corresponding RegPLDTableX with the wanted truth table. As mentioned in RegPLDMode description, using PLD 2-to-1 mode on I/0[0-2] implies to fill the truth table located in RegPLDTable0(3:0) I/O[ Rev 2 – 30 August 2010 I/O[0] I/O[ => RegPLDTable0 = “xxxx1000” SX1504/SX1505/SX1506 4/8/16 Channel GPIO www.semtech.com ...
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... Channel GPIO Default * 1111 1111 1111 1111 0000 0000 0000 0000 XXXX XXXX 1111 1111 XXXX XXXX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 XXXX XXXX 0000 0000 XXXX XXXX XXXX XXXX 00 : None 01 : Rising 10 : Falling 11 : Both www.semtech.com ...
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... Applies only when PLDMode is set to PLD 3-to-1 mode Default * 1111 1111 1111 1111 0000 0000 0000 0000 XXXX XXXX 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 www.semtech.com ...
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... Applies only when PLDModeHigh is set to PLD 2- to-1 mode Applies only when PLDModeLow is set to PLD 2- to-1 mode Applies only when PLDModeHigh is set to PLD 3- to-1 mode Applies only when PLDModeLow is set to PLD 3- to-1 mode Applies only when PLDModeLow is set to PLD 3- to-2 mode www.semtech.com ...
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... Description www.semtech.com * * ...
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... Writing '1' clears the bit in RegEventStatusA and in RegInterruptSourceA if relevant. If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically 7:6 Reserved. Must be set to 0 (default value) 23 SX1504/SX1505/SX1506 4/8/16 Channel GPIO Description 00 : None 01 : Rising 10 : Falling 11 : Both 00 : None 01 : Rising 10 : Falling 11 : Both 00 : None 01 : Rising 10 : Falling 11 : Both 00 : None 01 : Rising 10 : Falling 11 : Both www.semtech.com ...
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... Applies only when PLDModeHighA is set to PLD 2-to-1 mode Applies only when PLDModeLowA is set to PLD 2-to-1 mode Applies only when PLDModeHighB is set to PLD 3-to-1 mode Applies only when PLDModeHighA is set to PLD 3-to-1 mode Applies only when PLDModeLowB is set to PLD 3-to-1 mode www.semtech.com ...
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... Applies only when PLDModeLowA is set to PLD 3-to-1 mode Applies only when PLDModeLowB is set to PLD 3-to-2 mode Applies only when PLDModeLowA is set to PLD 3-to-2 mode Applies only when PLDModeLowB is set to PLD 3-to-2 mode Applies only when PLDModeLowA is set to PLD 3-to-2 mode www.semtech.com ...
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... LED colour/technology dependent Figure 13 – Typical LED Operation RegDir[x] “0” (Output) Table 17 – LED ON/OFF Control 26 SX1504/SX1505/SX1506 4/8/16 Channel GPIO 2.5V VCC1 5V 5V I/O[0] I/O[1] I/O[2] I/O[3] 5.5V VCC2 I/O[4] I/O[5] I/O[6] I/O[7] NINT * RegData[x] “0” “1” www.semtech.com ...
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... I/O bank) This can save significant BOM cost in a final application where only a few slow signals need to be level-shifted. th Rev 2 – 30 August 2010 SX1502 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 27 SX1504/SX1505/SX1506 4/8/16 Channel GPIO www.semtech.com ...
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... ACKAGING NFORMATION 7.1 QFN-UT 20-pin Outline Drawing QFN-UT 20-pin mm, 0.4 mm pitch Figure 15 - Packaging Information – QFN-UT 20-pin Outline Drawing 7.2 QFN-UT 20-pin Land Pattern Figure 16 - Packaging Information – QFN-UT 20-pin Land Pattern th Rev 2 – 30 August 2010 SX1504/SX1505/SX1506 4/8/16 Channel GPIO 28 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING 7.3 QFN-UT 28-pin Outline Drawing QFN-UT 28-pin mm, 0.4 mm pitch Figure 17 - Packaging Information – QFN-UT 28-pin Outline Drawing 7.4 QFN-UT 28-pin Land Pattern Figure 18 - Packaging Information – QFN-UT 28-pin Land Pattern th Rev 2 – 30 August 2010 SX1504/SX1505/SX1506 4/8/16 Channel GPIO 29 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING 7.5 TSSOP 20-pin Outline Drawing Figure 19 - Packaging Information – TSSOP 20-pin Outline Drawing 7.6 TSSOP 20-pin Land Pattern Figure 20 - Packaging Information – TSSOP 20-pin Land Pattern th Rev 2 – 30 August 2010 SX1504/SX1505/SX1506 4/8/16 Channel GPIO 30 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING 7.7 TSSOP 28-pin Outline Drawing Figure 21 - Packaging Information – TSSOP 28-pin Outline Drawing 7.8 TSSOP 28-pin Land Pattern Figure 22 - Packaging Information – TSSOP 28-pin Land Pattern th Rev 2 – 30 August 2010 SX1504/SX1505/SX1506 4/8/16 Channel GPIO 31 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING OLDERING ROFILE The soldering reflow profile for the SX1504, SX1505 and SX1506 is described in the standard IPC/JEDEC J- STD-020C. For detailed information please go to Figure 23 - Classification Reflow Profile (IPC/JEDEC J-STD-020C) th Rev 2 – 30 August 2010 SX1504/SX1505/SX1506 4/8/16 Channel GPIO http://www.jedec.org/download/search/jstd020c.pdf 32 www.semtech.com ...
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