SX1502I087TRT Semtech, SX1502I087TRT Datasheet
SX1502I087TRT
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SX1502I087TRT Summary of contents
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... SX1502I088TRT 8 (1) SX1503I089TRT 16 (2) SX1502EVK 8 (1) Future products (2) SX1502I087TRT based, unique evaluation kit for the three parts. th Rev 9 – 5 August 2010 4/8/16 Channel Low Voltage GPIO RODUCT 4/8/16 channel of I/ interface. 1.2V to 5.5V independent operating voltage for all supply rails (VDDM, VCC1, VCC2) 5 ...
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... NFORMATION 6.1 Typical Application Circuit 6.2 Typical LED Operation 6.2.1 LED ON/OFF Control 6.2.2 LED Intensity Control 6.3 Keypad Implementation 6.4 Level Shifter Implementation Hints th Rev 9 – 5 August 2010 4/8/16 Channel Low Voltage GPIO Table of Contents ............................................................................................... 7 ............................................................................... 10 ............................................................................................. 13 .................................................................................................. 20 ................................................................................................... 27 2 SX1501/SX1502/SX1503 www.semtech.com ...
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... QFN-UT 28-pin Outline Drawing 7.4 QFN-UT 28-pin Land Pattern 7.5 TSSOP 20-pin Outline Drawing 7.6 TSSOP 20-pin Land Pattern 7.7 TSSOP 28-pin Outline Drawing 7.8 TSSOP 28-pin Land Pattern .............................................................................................................. 33 OLDERING ROFILE th Rev 9 – 5 August 2010 4/8/16 Channel Low Voltage GPIO ..................................................................................................... 29 3 SX1501/SX1502/SX1503 www.semtech.com ...
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... Leave open, not connected - Connect to VCC1 P Ground Pin - Leave open, not connected - Leave open, not connected 2 C interface Table 1 – SX1501 Pin Description SDA NC1 SCL GND (PAD) I/O[0] Figure 1 – SX1501 QFN-UT-20 Pinout 4 SX1501/SX1502/SX1503 NC3 VDDM NC2 ADDR NINT www.semtech.com ...
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... Supply voltage for Bank B I/O[4-7] P Ground Pin (*1) DIO I/O[6], at power-on configured as an input (*1) DIO I/O[7], at power-on configured as an input 2 C interface Table 2 – SX1502 Pin Description SDA NC1 SCL GND (PAD) I/O[0] Figure 2 – SX1502 QFN-UT-20 Pinout 5 SX1501/SX1502/SX1503 I/O[4] VDDM NC2 ADDR NINT www.semtech.com ...
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... I/O[0], at power-on configured as an input (*1) DIO I/O[1], at power-on configured as an input 2 C interface Table 3 – SX1503 Pin Description 1 GND 2 I/O[2] TOP VIEW 3 I/O[3] GND VCC1 4 (PAD) I/O[4] 5 I/O[5] 6 GND 7 Figure 3 – SX1503 QFN-UT-28 Pinout 6 SX1501/SX1502/SX1503 21 GND 20 I/O[13] I/O[12] 19 VCC2 18 I/O[11] 17 I/O[10] 16 GND 15 www.semtech.com ...
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... V -40 +85 ° C -40 +125 ° C -55 +150 ° C +/-100 - mA Min Typ Max Unit 1.2 - 5.5 1 µ µA - 0.5 1 0.7* VCC1,2 - VCC1,2 +0.3 0.3* -0.4 - VCC1,2 0. VCC1,2 -1.5 - 1.5 µ VCC1,2 - VCC1,2 V – 0.3 -0 µ 1 0 www.semtech.com µs ...
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... VDDM -1 0.7 - 0.9 - VDDM 0 300 - - 0.7* VDDM - VDDM +0.3 0.3* -0.4 - VDDM 0. VDDM -1 specification version 2 0 0.7* - 5.5 VDDM 0.3* -0.4 - VDDM 0 - 400 (4) ( 0.9 (6) 100 - - (7) 20+0.1C - 300 b www.semtech.com µ µ µ kHz µs µs µs µs µs ns ...
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... SCL signal. LOW 250 ns must then be met. SU;DAT + t = 1000 + 250 r max SU;DAT Min Typ Max Unit 2.0 2.2 2.4 - 150 250 - 250 350 - 100 200 - 250 400 - 100 200 - 150 250 - 50 150 - 250 450 - 100 200 - - www.semtech.com ns µs µ µA uA µA µ ...
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... VOL vs. IOL 0.15 0.1 VOL (V) 0. Doesn’t vary significantly with temperature th Rev 9 – 5 August 2010 4/8/16 Channel Low Voltage GPIO IDDM vs VDDM VDDM (V) VOL vs IOL (VCC1,2=1.2V, all IOs) 1.5 4 IOL (mA) 10 SX1501/SX1502/SX1503 90° C -40° Tamb 7.5 9 www.semtech.com ...
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... Doesn’t vary significantly with temperature th Rev 9 – 5 August 2010 4/8/16 Channel Low Voltage GPIO VOL vs IOL (VCC1,2=5.5V, High Sink IOs IOL (mA) VOH vs IOH (VCC1,2=1.2V) 0.2 0.6 0.4 0.8 IOH (mA) VOH vs IOH (VCC1,2=5.5V) 10 IOH (mA) 11 SX1501/SX1502/SX1503 * Tamb Tamb 1 * Tamb 20 www.semtech.com ...
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... Rev 9 – 5 August 2010 4/8/16 Channel Low Voltage GPIO Boost Mode ON 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 VCC1,2 (V) Boost Mode ON 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 VCC1,2 (V) 12 SX1501/SX1502/SX1503 Tamb -40°C 90°C Tamb -40°C 90°C www.semtech.com ...
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... Figure 4 – 4-channel Low Voltage GPIO 2 8-Bit I C Bus Control R/W SX1502 GND Figure 5 – 8-channel Low Voltage GPIO 13 SX1501/SX1502/SX1503 VCC1 I/O[0] I/O Bank A I/O[1] A I/O[2] I/O[3] NINT Interrupt VCC1 I/O[0] I/O Bank A I/O[1] A I/O[2] I/O[3] VCC2 I/O[4] I/O Bank B I/O[5] A I/O[6] I/O[7] NINT Interrupt www.semtech.com ...
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... Figure 6 – 16-channel Low Voltage GPIO Undefined t PULSE . Chip can be accessed normally again after NRESET rising edge. 14 SX1501/SX1502/SX1503 VCC1 I/O[0] I/O[1] I/O[2] I/O Bank A I/O[3] A I/O[4] I/O[5] I/O[6] I/O[7] VCC2 I/O[8] I/O[9] I/O[10] I/O Bank B I/O[11] A I/O[12] I/O[13] I/O[14] I/O[15] NINT Interrupt Undefined t RESET www.semtech.com ...
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... C devices and comply with the Philips interface has been designed for program flexibility, in that once 2 C logic, a tight software loop can be designed then acknowledges that it is being addressed, and the master Slave Address: 7 bit Register Address: 8 bit Data: 8 bit 15 SX1501/SX1502/SX1503 2 C www.semtech.com ...
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... The slave acknowledges this request and returns the data from the register location that had previously been set up. th Rev 9 – 5 August 2010 4/8/16 Channel Low Voltage GPIO Figure 9 – Write RegData Register Slave Address: 7 bit Register Address: 8 bit Data: 8 bit 16 SX1501/SX1502/SX1503 2 C then www.semtech.com ...
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... August 2010 4/8/16 Channel Low Voltage GPIO Slave Address: 7 bit Register Address: 8 bit Data: 8 bit SX1501 I/Os 1 GPIO GPIO 01 GPIO PLD OUT PLD IN 10 PLD OUT PLD IN PLD IN Table 8 – SX1501 PLD Modes Settings 17 SX1501/SX1502/SX1503 1 0 GPIO GPIO PLD IN PLD IN www.semtech.com ...
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... GPIO GPIO GPIO PLD OUT PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN GPIO GPIO GPIO PLD OUT PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN GPIO GPIO GPIO PLD OUT PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN PLD IN www.semtech.com ...
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... What we need corresponds to the second line of the SX1502 PLD Table => RegPLDMode = “xx00xx01” 2. Fill corresponding RegPLDTableX with the wanted truth table. As mentioned in RegPLDMode description, using PLD 2-to-1 mode on I/0[0-2] implies to fill the truth table located in RegPLDTable0(3:0) I/O[ Rev 9 – 5 August 2010 4/8/16 Channel Low Voltage GPIO I/O[0] I/O[ => RegPLDTable0 = “xxxx1000” SX1501/SX1502/SX1503 www.semtech.com ...
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... SX1501/SX1502/SX1503 Default * 1111 1111 1111 1111 0000 0000 0000 0000 XXXX XXXX 1111 1111 XXXX XXXX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 XXXX XXXX 0000 0000 XXXX XXXX XXXX XXXX 0000 0000 00 : None 01 : Rising 10 : Falling 11 : Both www.semtech.com ...
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... Applies only when PLDMode is set to PLD 3-to-1 mode Default * 1111 1111 1111 1111 0000 0000 0000 0000 XXXX XXXX 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 www.semtech.com ...
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... None 01 : Rising 10 : Falling 11 : Both 00 : None 01 : Rising 10 : Falling 11 : Both Applies only when PLDModeHigh is set to PLD 2- to-1 mode Applies only when PLDModeLow is set to PLD 2- to-1 mode Applies only when PLDModeHigh is set to PLD 3- to-1 mode Applies only when PLDModeLow is set to PLD 3- to-1 mode www.semtech.com ...
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... Description www.semtech.com * * ...
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... Writing '1' clears the bit in RegEventStatusB and in RegInterruptSourceB if relevant. If the edge sensitivity of the IO is changed, the bit(s) will be cleared automatically 24 SX1501/SX1502/SX1503 Description 00 : None 01 : Rising 10 : Falling 11 : Both 00 : None 01 : Rising 10 : Falling 11 : Both 00 : None 01 : Rising 10 : Falling 11 : Both 00 : None 01 : Rising 10 : Falling 11 : Both www.semtech.com ...
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... Applies only when PLDModeHighA is set to PLD 2-to-1 mode Applies only when PLDModeLowA is set to PLD 2-to-1 mode Applies only when PLDModeHighB is set to PLD 3-to-1 mode Applies only when PLDModeHighA is set to PLD 3-to-1 mode Applies only when PLDModeLowB is set to PLD www.semtech.com ...
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... Applies only when PLDModeLowA is set to PLD 3-to-1 mode Applies only when PLDModeLowB is set to PLD 3-to-2 mode Applies only when PLDModeLowA is set to PLD 3-to-2 mode Applies only when PLDModeLowB is set to PLD 3-to-2 mode Applies only when PLDModeLowA is set to PLD 3-to-2 mode www.semtech.com ...
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... SX1501/2/3 R IOx IOL * LED colour/technology dependent Figure 13 – Typical LED Operation RegDir[x] “0” (Output) Table 18 – LED ON/OFF Control 27 SX1501/SX1502/SX1503 2.5V VCC1 5V 5V I/O[0] I/O[1] I/O[2] I/O[3] 1.2V VCC2 I/O[4] I/O[5] I/O[6] I/O[7] NINT * RegData[x] “0” “1” www.semtech.com ...
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... I/O bank) This can save significant BOM cost in a final application where only a few slow signals need to be level-shifted. th Rev 9 – 5 August 2010 4/8/16 Channel Low Voltage GPIO SX1502 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 28 SX1501/SX1502/SX1503 www.semtech.com ...
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... QFN-UT 20-pin Outline Drawing QFN-UT 20-pin mm, 0.4 mm pitch Figure 15 - Packaging Information – QFN-UT 20-pin Outline Drawing 7.2 QFN-UT 20-pin Land Pattern Figure 16 - Packaging Information – QFN-UT 20-pin Land Pattern th Rev 9 – 5 August 2010 SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO 29 www.semtech.com ...
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... QFN-UT 28-pin Outline Drawing QFN-UT 28-pin mm, 0.4 mm pitch Figure 17 - Packaging Information – QFN-UT 28-pin Outline Drawing 7.4 QFN-UT 28-pin Land Pattern Figure 18 - Packaging Information – QFN-UT 28-pin Land Pattern th Rev 9 – 5 August 2010 SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO 30 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING 7.5 TSSOP 20-pin Outline Drawing Figure 19 - Packaging Information – TSSOP 20-pin Outline Drawing 7.6 TSSOP 20-pin Land Pattern Figure 20 - Packaging Information – TSSOP 20-pin Land Pattern th Rev 9 – 5 August 2010 SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO 31 www.semtech.com ...
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... ADVANCED COMMUNICATIONS & SENSING 7.7 TSSOP 28-pin Outline Drawing Figure 21 - Packaging Information – TSSOP 28-pin Outline Drawing 7.8 TSSOP 28-pin Land Pattern Figure 22 - Packaging Information – TSSOP 28-pin Land Pattern th Rev 9 – 5 August 2010 SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO 32 www.semtech.com ...
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... OLDERING ROFILE The soldering reflow profile for the SX1501, SX1502 and SX1503 is described in the standard IPC/JEDEC J- STD-020C. For detailed information please go to Figure 23 - Classification Reflow Profile (IPC/JEDEC J-STD-020C) th Rev 9 – 5 August 2010 SX1501/SX1502/SX1503 4/8/16 Channel Low Voltage GPIO http://www.jedec.org/download/search/jstd020c.pdf 33 www.semtech.com ...
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