MCP23017-E/ML Microchip Technology, MCP23017-E/ML Datasheet
![IC I/O EXPANDER I2C 16B 28QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
MCP23017-E/ML
Specifications of MCP23017-E/ML
Available stocks
Related parts for MCP23017-E/ML
MCP23017-E/ML Summary of contents
Page 1
... I/O Expander with Serial Interface Features • 16-bit remote bidirectional I/O port - I/O pins default to input 2 • High-speed I C™ interface (MCP23017) - 100 kHz - 400 kHz - 1.7 MHz • High-speed SPI interface (MCP23S17 MHz (max.) • Three hardware address pins to allow up to eight devices on the bus • ...
Page 2
... MCP23017/MCP23S17 Functional Block Diagram CS SCK SI SPI SO SCL 2 I C™ SDA 3 A2:A0 Decode RESET INTA Interrupt INTB Logic DS21952B-page 2 MCP23S17 MCP23017 Serializer/ Deserializer Control 16 8 Configuration/ Control Registers GPB7 GPB6 GPB5 GPB4 GPIO GPB3 GPB2 GPB1 GPB0 GPA7 GPA6 GPA5 GPA4 GPIO ...
Page 3
... I C bus or SPI applications. The two devices differ only in the serial interface. 2 • MCP23017 – interface • MCP23S17 – SPI interface The MCP23X17 consists of multiple 8-bit configuration registers for input, output and polarity selection. The system master can enable the I/Os as either inputs or outputs by writing the I/O configuration bits (IODIRA/B) ...
Page 4
... Ground SS NC/ (MCP23017), Chip Select (MCP23S17) SCL/SCK Serial clock input SDA/ I/O Serial data I/O (MCP23017), Serial data input (MCP23S17) NC/ (MCP23017), Serial data out (MCP23S17 Hardware address pin. Must be externally biased Hardware address pin. Must be externally biased Hardware address pin. Must be externally biased. ...
Page 5
... INTCAPA Figure 1-1. This sequence is followed by eight bits of INTCAPB data from the master and an Acknowledge (ACK) from GPIOA the MCP23017. The operation is ended with a Stop (P) or Restart (SR) condition being generated by the GPIOB master. OLATA Data is written to the MCP23017 after every byte OLATB transfer ...
Page 6
... Section 1.3.1 “Byte Mode and Sequential Mode” for details regarding sequential operation control). The sequence ends with the master sending a Stop or Restart condition. The MCP23017 Address Pointer will roll over to address zero after reaching the last register address. Refer to Figure 1-1. ...
Page 7
... FIGURE 1-1: MCP23017 I C™ DEVICE PROTOCOL - Start S - Restart Stop P - Write w - Read R - Device opcode OP ADDR - Device register address D - Data out from MCP23017 OUT D - Data in to MCP23017 Byte S OP Sequential Byte S OP Sequential S OP © 2007 Microchip Technology Inc. MCP23017/MCP23S17 D W ADDR .... IN ...
Page 8
... The address pins should be externally biased even if disabled (IOCON.HAEN = 0). 2 FIGURE 1-4: I C™ ADDRESSING REGISTERS Device Opcode *The ACKs are provided by the MCP23017. FIGURE 1-5: SPI ADDRESSING REGISTERS Device Opcode * Address pins are enabled/disabled via IOCON.HAEN. DS21952B-page 8 FIGURE 1-2: ...
Page 9
... OLATB 15 OL7 OL6 © 2007 Microchip Technology Inc. MCP23017/MCP23S17 Reading the GPIOn register reads the value on the port. Reading the OLATn register only reads the latches, not the actual value on the port. Writing to the GPIOn register actually causes a write to the latches (OLATn). Writing to the OLATn register forces the associated output drivers to drive to the level in OLATn ...
Page 10
... MCP23017/MCP23S17 1.6 Configuration and Control Registers There are 21 registers associated with the MCP23X17, as shown in Table 1-5 and Table 1-6. The two tables show the register mapping with the two BANK bit values. Ten registers are associated with PortA and ten TABLE 1-5: CONTROL REGISTER SUMMARY (IOCON ...
Page 11
... ICP6 INTCAPB 11 ICP7 ICP6 GPIOA 12 GP7 GP6 GPIOB 13 GP7 GP6 OLATA 14 OL7 OL6 OLATB 15 OL7 OL6 © 2007 Microchip Technology Inc. MCP23017/MCP23S17 ) 0 bit 5 bit 4 bit 3 bit 2 IO5 IO4 IO3 IO2 IO5 IO4 IO3 IO2 IP5 IP4 IP3 IP2 IP5 IP4 IP3 ...
Page 12
... MCP23017/MCP23S17 1.6.1 I/O DIRECTION REGISTER Controls the direction of the data I/O. When a bit is set, the corresponding pin becomes an input. When a bit is clear, the corresponding pin becomes an output. REGISTER 1-1: IODIR – I/O DIRECTION REGISTER (ADDR 0x00) R/W-1 R/W-1 R/W-1 IO7 IO6 ...
Page 13
... IP7:IP0: These bits control the polarity inversion of the input pins <7:0> GPIO register bit will reflect the opposite logic state of the input pin GPIO register bit will reflect the same logic state of the input pin. © 2007 Microchip Technology Inc. MCP23017/MCP23S17 R/W-0 R/W-0 R/W-0 ...
Page 14
... MCP23017/MCP23S17 1.6.3 INTERRUPT-ON-CHANGE CONTROL REGISTER The GPINTEN register controls the interrupt-on- change feature for each pin bit is set, the corresponding pin is enabled for interrupt-on-change. The DEFVAL and INTCON registers must also be configured if any pins are enabled for interrupt-on-change. REGISTER 1-3: GPINTEN – INTERRUPT-ON-CHANGE PINS (ADDR 0x02) ...
Page 15
... DEF7:DEF0: These bits set the compare value for pins configured for interrupt-on-change from defaults <7:0>. Refer to INTCON. If the associated pin level is the opposite from the register bit, an interrupt occurs. Refer to INTCON and GPINTEN. © 2007 Microchip Technology Inc. MCP23017/MCP23S17 R/W-0 R/W-0 R/W-0 DEF4 ...
Page 16
... MCP23017/MCP23S17 1.6.5 INTERRUPT CONTROL REGISTER The INTCON register controls how the associated pin value is compared for the interrupt-on-change feature bit is set, the corresponding I/O pin is compared against the associated bit in the DEFVAL register bit value is clear, the corresponding I/O pin is compared against the previous value ...
Page 17
... For this reason advised to only perform byte writes to this register when changing the BANK bit. © 2007 Microchip Technology Inc. MCP23017/MCP23S17 The MIRROR bit controls how the INTA and INTB pins function with respect to each other. • When MIRROR = 1, the INTn pins are functionally OR’ ...
Page 18
... Slew rate disabled Slew rate enabled. bit 3 HAEN: Hardware Address Enable bit (MCP23S17 only). Address pins are always enabled on MCP23017 Enables the MCP23S17 address pins Disables the MCP23S17 address pins. bit 2 ODR: This bit configures the INT pin as an open-drain output. ...
Page 19
... Bit is set bit 7-0 PU7:PU0: These bits control the weak pull-up resistors on each pin (when configured as an input) <7:0> Pull-up enabled Pull-up disabled. © 2007 Microchip Technology Inc. MCP23017/MCP23S17 R/W-0 R/W-0 R/W-0 PU4 PU3 PU2 U = Unimplemented bit, read as ‘0’ ...
Page 20
... MCP23017/MCP23S17 1.6.8 INTERRUPT FLAG REGISTER The INTF register reflects the interrupt condition on the port pins of any pin that is enabled for interrupts via the GPINTEN register. A ‘set’ bit indicates that the associated pin caused the interrupt. This register is ‘read-only’. Writes to this register will be ignored ...
Page 21
... Bit is set bit 7-0 ICP7:ICP0: These bits reflect the logic level on the port pins at the time of interrupt due to pin change <7:0> Logic-high Logic-low. © 2007 Microchip Technology Inc. MCP23017/MCP23S17 R-x R-x R-x ICP4 ICP3 ICP2 U = Unimplemented bit, read as ‘0’ ...
Page 22
... MCP23017/MCP23S17 1.6.10 PORT REGISTER The GPIO register reflects the value on the port. Reading from this register reads the port. Writing to this register modifies the Output Latch (OLAT) register. REGISTER 1-10: GPIO – GENERAL PURPOSE I/O PORT REGISTER (ADDR 0x09) R/W-0 R/W-0 ...
Page 23
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 OL7:OL0: These bits reflect the logic level on the output latch <7:0> Logic-high Logic-low. © 2007 Microchip Technology Inc. MCP23017/MCP23S17 R/W-0 R/W-0 R/W-0 OL4 OL3 OL2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 24
... MCP23017/MCP23S17 1.7 Interrupt Logic If enabled, the MCP23X17 activates the INTn interrupt output when one of the port pins changes state or when a pin does not match the preconfigured default. Each pin is individually configurable as follows: • Enable/disable interrupt via GPINTEN • Can interrupt on either pin change or change from ...
Page 25
... FIGURE 1-6: INTERRUPT-ON-PIN CHANGE GPx INT ACTIVE Port value Read GPIO Port value is captured or INTCAP is captured into INTCAP into INTCAP © 2007 Microchip Technology Inc. MCP23017/MCP23S17 FIGURE 1-7: GP GP2 Pin INT Pin Port value is captured into INTCAP ACTIVE INTERRUPT-ON-CHANGE ...
Page 26
... MCP23017/MCP23S17 NOTES: DS21952B-page 26 © 2007 Microchip Technology Inc. ...
Page 27
... The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., out- side specified power supply range) and therefore outside the warranted range. © 2007 Microchip Technology Inc. MCP23017/MCP23S17 (except V )............................................................. -0. )...................................................................................................................... ± ...
Page 28
... MCP23017/MCP23S17 2.1 DC Characteristics Operating Conditions (unless otherwise indicated): 1.8V ≤ Characteristics 4.5V ≤ V Param Characteristic Sym No. D001 Supply Voltage V DD D002 V Start Voltage POR Ensure Power-on Reset D003 V Rise Rate Ensure Power-on Reset D004 Supply Current I DD D005 Standby current I DDS ...
Page 29
... FIGURE 2-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS SCL and SDA pin MCP23017 FIGURE 2-2: RESET AND DEVICE RESET TIMER TIMING V DD RESET Internal RESET Output pin © 2007 Microchip Technology Inc. MCP23017/MCP23S17 V DD Pin 1 kΩ 135 DS21952B-page 29 ...
Page 30
... MCP23017/MCP23S17 TABLE 2-1: DEVICE RESET SPECIFICATIONS Operating Conditions (unless otherwise indicated): 1.8V ≤ Characteristics 4.5V ≤ V Param Characteristic No. 30 RESET Pulse Width (Low) 32 Device Active After Reset high 34 Output High-Impedance From RESET Low Note 1: This parameter is characterized, not 100% tested. 2 FIGURE 2-3: I C™ ...
Page 31
... MHz mode Note 1: This parameter is characterized, not 100% tested specified to be from 10 to 400 pF. B © 2007 Microchip Technology Inc. MCP23017/MCP23S17 Operating Conditions (unless otherwise indicated): 1.8V ≤ V ≤ 5.5V at -40°C ≤ T ≤ +85°C (I-Temp 4.5V ≤ V ≤ 5.5V at -40°C ≤ T ≤ ...
Page 32
... MCP23017/MCP23S17 2 TABLE 2-2: I C™ BUS DATA REQUIREMENTS (CONTINUED C™ AC Characteristics Param Characteristic No. 109 Output Valid From Clock: 100 kHz mode 400 kHz mode 1.7 MHz mode 110 Bus Free Time: 100 kHz mode 400 kHz mode 1.7 MHz mode Bus Capacitive Loading: 100 kHz and 400 kHz 1 ...
Page 33
... CLK Rise Time 7 CLK Fall Time 8 Clock High Time Note 1: This parameter is characterized, not 100% tested. © 2007 Microchip Technology Inc. MCP23017/MCP23S17 13 Don’t Care Operating Conditions (unless otherwise indicated): 1.8V ≤ V ≤ 5.5V at -40°C ≤ T ≤ +85°C (I-Temp 4.5V ≤ V ≤ ...
Page 34
... MCP23017/MCP23S17 TABLE 2-3: SPI INTERFACE AC CHARACTERISTICS (CONTINUED) SPI Interface AC Characteristics Param Characteristic No. 9 Clock Low Time 10 Clock Delay Time 11 Clock Enable Time 12 Output Valid from Clock Low 13 Output Hold Time 14 Output Disable Time Note 1: This parameter is characterized, not 100% tested. FIGURE 2-7: ...
Page 35
... GP Input Change to Register Valid 53 IOC Event to INT Active Glitch Filter on GP Pins Note 1: This parameter is characterized, not 100% tested © 2007 Microchip Technology Inc. MCP23017/MCP23S17 Operating Conditions (unless otherwise indicated): 1.8V ≤ V ≤ 5.5V at -40°C ≤ T ≤ +85°C (I-Temp 4.5V ≤ V ≤ ...
Page 36
... MCP23017/MCP23S17 NOTES: DS21952B-page 36 © 2007 Microchip Technology Inc. ...
Page 37
... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007 Microchip Technology Inc. MCP23017/MCP23S17 Example: MCP23017-E/SP 0648256 Example: 23017 E/ 0648256 Example: MCP23017-E/SO 0648256 Example: MCP23017 e E/SS^^ 3 0648256 ) e 3 DS21952B-page 37 ...
Page 38
... MCP23017/MCP23S17 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width ...
Page 39
... Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2007 Microchip Technology Inc. MCP23017/MCP23S17 EXPOSED PAD ...
Page 40
... MCP23017/MCP23S17 28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N NOTE Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width ...
Page 41
... Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2007 Microchip Technology Inc. MCP23017/MCP23S17 ...
Page 42
... MCP23017/MCP23S17 NOTES: DS21952B-page 42 © 2007 Microchip Technology Inc. ...
Page 43
... Table 2-4, Param No. 51 and 53: Changed from 450 to 600 and 500 to 600, respecively. 3. Added disclaimers to package outline drawings. 4. Updated package outline drawings. Revision A (June 2005) • Original Release of this Document. © 2007 Microchip Technology Inc. MCP23017/MCP23S17 Read in DS21952B-page 39 ...
Page 44
... MCP23017/MCP23S17 NOTES: DS21952B-page 40 © 2007 Microchip Technology Inc. ...
Page 45
... Plastic SOIC (300 mil Body), 28-Lead SS = SSOP, (209 mil Body, 5.30 mm), 28-Lead © 2007 Microchip Technology Inc. MCP23017/MCP23S17 . Examples: a) MCP23017-E/SP: b) MCP23017-E/SO: Extended Temp MCP23017T-E/SO: Tape and Reel, C™ Interface 2 C Interface d) MCP23017-E/SS: e) MCP23017T-E/SS: Tape and Reel, a) MCP23S17-E/SP: Extended Temp., b) MCP23S17-E/SO: Extended Temp., c) MCP23S17T-E/SO: Tape and Reel, d) MCP23S17-E/SS: Extended Temp ...
Page 46
... MCP23017/MCP23S17 NOTES: DS21952B-page 42 © 2007 Microchip Technology Inc. ...
Page 47
... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
Page 48
... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...