MAX7326AEG+T Maxim Integrated Products, MAX7326AEG+T Datasheet - Page 10

• Manufacturer Part Number: MAX7326AEG+T
• Description: IC I/O EXPANDER I2C 16B 24QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX7326AEG+T

• Interface: I²C
• Number Of I /o: 16
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-QSOP
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
and 4 Inputs
The MAX7326 operates as a slave that sends and
receives data through an I
uses a serial-data line (SDA) and a serial-clock line (SCL)
to achieve bidirectional communication between mas-
ter(s) and slave(s). The master initiates all data transfers
to and from the MAX7326 and generates the SCL clock
that synchronizes the data transfer (Figure 1).
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically 4.7kΩ, is required on
SDA. SCL operates only as an input. A pullup resistor,
typically 4.7kΩ, is required on SCL if there are multiple
masters on the 2-wire interface, or if the master in a sin-
gle-master system has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7326’s 7-bit slave
Figure 1. 2-Wire Serial-Interface Timing Details
Figure 2. START and STOP Conditions
10
2
SDA
SCL
C Port Expander with 12 Push-Pull Outputs
CONDITION
______________________________________________________________________________________
START
S
SDA
SCL
t
HD,STA
START CONDITION
t
LOW
2
C interface. The interface
t
R
t
SU,DAT
t
HIGH
Serial Interface
Serial Addressing
t
F
t
HD,DAT
CONDITION
STOP
P
t
REPEATED START CONDITION
SU,STA
addresses plus R/W bits, 1 or more data bytes, and
finally a STOP condition (Figure 2).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 2).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 3).
Figure 3. Bit Transfer
SDA
SCL
t
HD,STA
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
START and STOP Conditions
t
SU,STO
CONDITION
STOP
t
BUF
CONDITION
START
Bit Transfer