C200HW-CE002 Omron, C200HW-CE002 Datasheet - Page 109
![no-image](/images/manufacturer_photos/0/4/494/omron_sml.jpg)
C200HW-CE002
Manufacturer Part Number
C200HW-CE002
Description
DOUBLE CPU BUS
Manufacturer
Omron
Datasheet
1.C1000H-COV01.pdf
(153 pages)
Specifications of C200HW-CE002
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
C200HWCE002
- Current page: 109 of 153
- Download datasheet (9Mb)
106
PROGRAMMING INSTRUCTIONS
DATA SHIFTING INSTRUCTIONS
NAME MNEMONIC
SHIFT REGISTER
SFT(10)
REVERSIBLE SHIFT
REGISTER
(@)SFTR(84)
ASYNCHRONOUS SHIFT REG-
ISTER
(@)ASFT(17)
WORD SHIFT
(@)WSFT(16)
ARITHMETIC SHIFT LEFT
(@)ASL(25)
ARITHMETIC SHIFT RIGHT
(@)ASR(26)
An instruction marked with “@” can be used as a differentiated instruction that will be executed only once each time the instruction
executing condition is turned ON.
An instruction marked with “
An instruction marked with “
” is an expansion instruction. These instructions must be assigned function codes before they can be used.
” is an expansion instruction. The assigned function code is the default for the C200HX/HG/HE PLC.
SYMBOL
I
P
R
WSFT(16)
ASFT(17)
SFTR(84)
ASL(25)
ASR(26)
SFT(10)
Wd
Wd
St
St
C
E
E
St
St
E
C
E
Shifts bits in the specified words either left or right.
Starting (St) and ending words (E) must be specified.
IN
FUNCTION
Creates a bit shift register for data from the starting
word (St) through to the ending word (E).
15
Creates and controls a reversible non-synchronous
word shift register between St and E. Exchanges the
content of a word containing zero with the content of ei-
ther the preceding or following word, depending on the
shift direction.
The data in the words from the starting word (St)
through to the ending word (E), is shifted left in word
units, writing all zeros into the starting word.
Each bit within a single word of data (Wd) is shifted one
bit to the left, with zero written to bit 00 and bit 15 moving
to CY.
Each bit within a single word of data (Wd) is shifted one
bit to the right, with zero written to bit 15 and bit 00 mov-
ing to CY.
0
CY
15
15
CY
15
E
E
E
00
15
00
Wd
00
Wd
15
00
15
S
t
St
CY
00
00
00
CY
15
IN
0
St
00
IN