DS90CR482VSX National Semiconductor, DS90CR482VSX Datasheet - Page 11
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DS90CR482VSX
Manufacturer Part Number
DS90CR482VSX
Description
Manufacturer
National Semiconductor
Datasheet
1.DS90CR482VSX.pdf
(21 pages)
Specifications of DS90CR482VSX
Number Of Elements
8
Number Of Receivers
8
Number Of Drivers
48
Input Type
CMOS/TTL
Operating Supply Voltage (typ)
3.3V
Differential Input High Threshold Voltage
100mV
Diff. Input Low Threshold Volt
-100mV
Output Type
Deserializer
Transmission Data Rate
5376Mbps
Power Dissipation
2.3W
Operating Temp Range
-10C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS90CR482VSX/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
AC Timing Diagrams
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
See Applications Information section for more details.
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
RSKMD ≥ TPPOSvariance (d) + TJCC (output jitter)(f) + ISI (m)
See Applications Informations section for more details.
j
j
j
j
j
j
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
ISI is dependent on interconnect length; may be zero
d= Tppos — Transmitter output pulse position (min and max)
f= Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate)
m= extra margin - assigned to ISI in long cable applications
FIGURE 13. Receiver Skew Margin (RSKM) for Chipset without DESKEW
FIGURE 14. Receiver Skew Margin (RSKMD) for Chipset with DESKEW
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