QT60486-AS Atmel, QT60486-AS Datasheet - Page 6

• Manufacturer Part Number: QT60486-AS
• Description: SENSOR IC MTRX TOUCH48KEY 44TQFP
• Manufacturer: Atmel
• Series: QMatrix™, QProx™r
• Type: Capacitiver

Specifications of QT60486-AS

• Rohs Status: RoHS non-compliant
• Number Of Inputs/keys: 48 Key
• Resolution (bits): 9, 11 b
• Data Interface: Serial, SPI™, UART
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 25mA
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 44-TQFP, 44-VQFP
• Output Type: *
• Interface: *
• Input Type: *
• For Use With: 427-1088 - BOARD EVAL QT60486-AS QMATRIX

3 Serial Communications
These devices can use either SPI or UART communications
modes; it cannot use both at the same time. The mode
selected depends on which mode is used first to
communicate with the part.
The host device always initiates communications sequences;
the QT is incapable of chattering data back to the host. This is
intentional for FMEA purposes so that the host always has
total control over the communications with the QT60xx6.
A command from the host always ends in a response of some
kind from the QT. Some transmission types from the host or
the QT employ a CRC check byte to provide for robust
communications.
A DRDY line is provided that handshakes transmissions.
Generally this is needed by the host from the QT to ensure
that transmissions are not sent when the QT is busy or has
not yet processed a prior command. In UART mode this line
is bi-directional, and the QT can use it to suspend
transmissions back to the host if the host is busy.
3.1 DRDY Line
Serial communications is controlled by the DRDY line, which
is an output from the QT60xx6 to the host. When DRDY is
high, the host is permitted to send data. This works in both
UART and SPI modes. After a byte is received DRDY will
always go low even if only for a few microseconds; during this
period the host should not send data. Therefore, after each
byte transmission the host should first check that DRDY is
high again.
The host should sequence transmissions as follows:
DRDY is an open-drain output which must be pulled high by
an external resistor, from 10K ~ 50K ohms in either UART or
SPI mode.
3.2 SPI Communications
SPI mode is selected if the host sends data over the SPI lines
first. There is no other configuration required to make the
device operate in SPI mode. Once SPI is selected after a
lQ
Advanced information; subject to change
1. Check to see if DRDY is high; if not, wait
2. If DRDY is high: send a byte to QT
3. Wait 100µs or longer (time T2)
4. Wait until DRDY is high (it may already be high)
5. Send next command or null byte to QT
(Slave Input - MOSI)
(Slave Out - MISO)
Host Data Output
QT Data Output
CLK from Host
DRDY from QT
/SS from host
3-state
?
high via pullup-R
?
Data shifts out on falling edge
7
7
Data shifts in on rising edge
T1
6
6
command byte
5
5
4
4
3
3
2
2
1
1
0
0
Figure 3-2 SPI Slave-Only Mode Timing
3-state
T2
Twcrdy
? 7
7
6
6
6
optional 2nd command byte
powerup, the device cannot switch to UART mode unless the
device is reset.
SPI communications operates in slave mode only, and obeys
DRDY control signaling. The clocking is as follows:
SPI mode requires 5 signals to operate:
MOSI - Master out / Slave in data pin; used as an input for
MISO - Master in / Slave out data pin; used as an output for
SCK - SPI clock - input only clock pin from host. The host
/SS - Slave select - input only; acts as a framing signal to the
DRDY - Data Ready - active-high - indicates to the host that
5
5
T3
data from the host (master). This pin should be connected
to the MOSI (DO) pin of the host device.
data to the host. This pin should be connected to the MISO
(DI) pin of the host.
must shift out data on the falling edge of SCK; the QT60xx6
clocks data in on the rising edge of SCK. The QT60xx6
likewise shifts data out on the rising edge back to the host.
Important note: SCK must idle high; SCK should never
float.
sensor from the host. /SS must be low before and during
reception of data from the host. It must not go high again
until the SCK line has returned high; /SS must idle high.
the QT is ready to send or receive data. This pin idles high.
DRDY should be pulled high with a 10K to 100K pullup
resistor. In SPI mode this pin is an output only.
4
4
3
3
2
2
Clock idle:
Clock shift out edge:
Clock data in edge:
Max clock rate:
T4
1
1
0
0
Tcyc
Host MCU
Figure 3-1 SPI Connections
P_OUT
MISO
MOSI
P_IN
SCK
10K
Vdd
High
Falling
Rising
4MHz
QT60486-AS 0.07/1103
?
7
7
null byte to get QT response
QT60xx6
6
6
DRDY
SS
SCK
MISO
MOSI
data response
5
5
4
4
3
3
2
2
1
1
0
0