DS32EL0124SQ/NOPB National Semiconductor, DS32EL0124SQ/NOPB Datasheet

IC DESERIAL W/DDR LVDS 48LLP

DS32EL0124SQ/NOPB

Manufacturer Part Number
DS32EL0124SQ/NOPB
Description
IC DESERIAL W/DDR LVDS 48LLP
Manufacturer
National Semiconductor
Datasheet

Specifications of DS32EL0124SQ/NOPB

Function
Deserializer
Data Rate
3.125Gbps
Input Type
LVDS
Output Type
LVDS
Number Of Inputs
5
Number Of Outputs
1
Voltage - Supply
2.5V, 3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LLP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DS32EL0124SQ
© 2011 National Semiconductor Corporation
125 MHz - 312.5 MHz FPGA-Link Deserializer with DDR
LVDS Parallel Interface
General Description
The DS32EL0124/DS32ELX0124 integrates clock and data
recovery modules for high-speed serial communication over
FR-4 printed circuit board backplanes, balanced cables, and
optical fiber. This easy-to-use chipset integrates advanced
signal and clock conditioning functions, with an FPGA friendly
interface.
The DS32EL0124/DS32ELX0124 deserializes up to 3.125
Gbps of high speed serial data to 5 LVDS outputs without the
need for an external reference clock. With DC-balance de-
coding enabled, the application payload of 2.5 Gbps is dese-
rialized to 4 LVDS outputs.
The DS32EL0124/DS32ELX01214 deserializers feature a re-
mote sense capability to automatically signal link status con-
ditions to its companion DS32EL0421/ELX0421 serializers
without requiring an additional feedback path.
The parallel LVDS interface of these devices reduce FPGA
I/O pins, board trace count and alleviates EMI issues, when
compared to traditional single-ended wide bus interfaces.
The DS32EL0124/ELX0124 is programmable through a SM-
Bus interface as well as through control pins.
Applications
Typical Application
Imaging: Industrial, Medical Security, Printers
Displays: LED walls, Commercial
Video Transport
Communication Systems
Test and Measurement
Industrial Bus
DS32EL0124, DS32ELX0124
300431
Features
Key Specifications
5-bit DDR LVDS parallel data interface
Programmable Receive Equalization
Selectable DC-balance decoder
Selectable De-scrambler
Remote Sense for automatic detection and negotiation of
link status
No external receiver reference clock required
LVDS parallel interface
Programmable LVDS output clock delay
Supports output data-valid signaling
Supports keep-alive clock output
On chip LC VCOs
Redundant serial input (ELX device only)
Retimed serial output (ELX device only)
Configurable PLL loop bandwidth
Configurable via SMBus
Loss of lock and error reporting
48-pin LLP package with exposed DAP
1.25 to 3.125 Gbps serial data rate
125 to 312.5 MHz DDR parallel clock
-40° to +85°C temperature range
> 8 kV ESD (HBM) protection
0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps)
www.national.com
April 7, 2011
30043101

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DS32EL0124SQ/NOPB Summary of contents

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... Displays: LED walls, Commercial ■ Video Transport ■ Communication Systems ■ Test and Measurement ■ Industrial Bus Typical Application © 2011 National Semiconductor Corporation DS32EL0124, DS32ELX0124 Features ■ 5-bit DDR LVDS parallel data interface ■ Programmable Receive Equalization ■ Selectable DC-balance decoder ■ ...

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Connection Diagrams NSID Description DS32EL0124SQ DES DS32EL0124SQE DS32EL0124SQX DS32ELX0124SQ DES with Redundant Input and Retimed Output DS32ELX0124SQE DS32ELX0124SQX www.national.com Ordering Information Package 48 - LLP, SQA48A 48 - LLP, SQA48A 48 - LLP, SQA48A 48 - LLP, SQA48A 48 - ...

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Pin Descriptions Pin Name Pin Number VDD33 1, 15, 18, 36 VDD25 7, 25, 35 VDD_PLL 28 LF_CP 27 LF_REF 26 Exposed Pad 49 I/O, Type Description I, VDD 3.3V supply I, VDD 2.5V supply I, VDD 3.3V supply Analog ...

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Pin Name Pin Number CML I/O RxIN0+ 16 RxIN0- 17 RxIN1+ 19 RxIN1- 20 TxOUT+ 21 TxOUT- 22 LVDS Parallel Data Bus RxCLKOUT+ 37 RxCLKOUT- 38 RxOUT[0:4]+/- 39, 40, 41, 42, 43, 44, 45, 46, 47, 48 Control Pins LT_EN ...

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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V ) DD33 Supply Voltage (V ) DD25 LVCMOS Input Voltage LVCMOS Output Voltage CML Input/Output Voltage LVDS Output Voltage Junction Temperature Storage Temperature Range Lead Temperature Range Soldering (4 sec ...

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LVCMOS Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Applies to LT_EN, GPIO0, GPIO1, GPIO2, RX_MUX_SEL, DC_B, RESET, RS, LOCK. Symbol Parameter V High Level Input Voltage IH V Low Level Input Voltage IL V High ...

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LVDS Electrical Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter V Differential Output Voltage OD Changes in V between complimentary output Δ states V Offset Voltage OS ΔV Change in V between complimentary ...

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CML Input Timing Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter TOL Serial Input Jitter Tolerance JIT CML Input Electrical Specifications Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter V Differential ...

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Note 4: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except V Δ Note 5: Typical values represent most likely parametric norms for ...

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FIGURE 4. Reset to Lock Time FIGURE 5. Deserializer Propagation Delay FIGURE 6. CML to LVDS Bit Map 10 30043114 30043113 30043104 ...

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Functional Description POWER SUPPLIES The DS32EL0124 and DS32ELX0124 have several power supply pins, at 2.5V as well as 3.3V important that these pins all be connected and properly bypassed. Bypassing should consist of parallel 4.7μF and 0.1μF capacitors ...

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DESCRAMBLER AND NRZI DECODER The CDR of the deserializer expects a transition density of 20% for a period of 200 μs. To improve the transition density of the data, the scrambler and NRZI encoder, which are inte- grated features in ...

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DC-coupled where there is no significant Ground potential difference between the interfacing systems. The serial inputs also provides input equalization control in order to compensate for loss from the media. The level of equalization is controlled ...

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SMBus INTERFACE The System Management Bus interface is compatible to SM- Bus 2.0 physical layer specification. The use of the Chip Select signal is required. Holding the SMB_CS pin HIGH en- ables the SMBus port, allowing access to the configuration ...

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FIGURE 8. SMBus Configuration 1 FIGURE 9. SMBus Configuration 2 15 30043107 30043108 www.national.com ...

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PROPAGATION DELAY Once the deserializer is locked, the amount of time it takes for a signal to travel from the high speed CML serial input through the device and out via the DDR LVDS interface is defined to be the ...

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Applications Information GPIO PINS The GPIO pins can be useful tools when debugging or eval- uating the system. For specific GPIO configurations and func- tions refer to registers and 6 in the device register map. GPIO ...

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FIGURE 12. Typical Interface Circuit 18 30043105 ...

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Typical Performance Characteristics The eye diagrams shown below illustrate the typical perfor- mace of the DS32ELX0124/DS32EL0124 configured with DC_B = 0, for the conditions listed below each figure. The PRBS-15 data was generated by a low cost ...

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Retimed Loop Through Output (1.25 Gbps, 40m CAT-5e, 0x000 DS32ELX0124 EQ setting, 0x10 DS32EL0421 De-Emphasis setting) www.national.com 30043122 Retimed Loop Through Output (3.125 Gbps, 20m CAT-6 SCTP, 0x001 DS32ELX0124 EQ setting, 0x10 DS32EL0421 De-Emphasis setting) 20 30043123 ...

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Register Map The register information for the deserializer is shown in the table below. Some registers have been omitted or marked as Addr (Hex) Name 00 Device ID 01 Reset 02 GPIO0 Config 03 GPIO1 Config 04 GPIO2 Config 05 ...

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Addr (Hex) Name 06 GP Out 07 — 1F Reserved 20 Device Config 0 21 Device Config 1 22 Device Config Override 23 — 26 Reserved www.national.com Bits Field R/W Default 7:3 Reserved 2 GP Out 2 R ...

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Addr (Hex) Name 27 LVDS Per Channel Enable 28 LVDS Config 29 — 2A Reserved 2B Event Config 2C Reserved 2D Error Monitor 2E Error Threshold LSBs 2F Error Threshold MSBs Bits Field R/W Default 7 LVDS V High R/W ...

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Addr (Hex) Name 30 — 3A Reserved 3B Data Rate 3C Reserved 3D Event Status 3E Error Status LSBs 3F Errors Status MSBs 40 — 49 Reserved 49 Loop Through Driver Config 7 Attenuator www.national.com Bits Field R/W ...

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Addr (Hex) Name 61 EQ Boost Control 62 Reserved 63 EQ Override Control 64 — 66 Reserved 67 LT De-Emphasis Control Bits Field R/W Default 7 Boost Control 4 Boost Control 1:0 Reserved 7 Reserved 6 ...

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Physical Dimensions (See AN-1187 for PCB Design and Assembly Recommendations) www.national.com inches (millimeters) unless otherwise noted NS Package Number SQA48A 26 ...

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Notes 27 www.national.com ...

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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...

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