NJU3712D NJR, NJU3712D Datasheet - Page 3
Manufacturer Part Number
IC 8BIT SRL TO PRL CONVTR 16DIP
Specifications of NJU3712D
Serial to Parallel
Number Of Inputs
Number Of Outputs
Voltage - Supply
4.5 V ~ 5.5 V
-25°C ~ 85°C
Package / Case
16-DIP (0.325", 8.25mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
(2) Data Transmission
(3) Cascade Connection
output are "L" level.
into the DATA terminal are shifted in the shift register synchronizing at a rising edge of the clock signal.
the clock signal should be controlled for data order.
unrelated with the CLR and STB status.
to protect the noise.
When the "L" level is input to the CLR terminal, all latches are reset and all of parallel conversion
Normally, the CLR terminal should be "H" level.
In the STB terminal is "H" level and the clock signals are inputted to the CLK terminal, the serial data
When the STB terminal is changed to "L" level, the data in the shift register are transferred to the
Even if the STB terminal is "L" level, the input clock signal shifts the data in the shift register, therefore,
The serial data input from DATA terminal is output from the SO terminal through internal shift register
Furthermore, the 4 input circuits provide a hysteresis characteristics using the schmitt trigger structure
X: Don’t care
All of latches are reset (the data in the shift register is no change).
All of parallel conversion outputs are "L".
The data in the shift register is transferred to the latch. And the data in the
latch is output from the parallel conversion output terminals.
When the clock signal is inputted into the CLK terminal in state of the
STB="L" and CLR="H", the data is shifted in the shift register and latched
data is also changed in accordance with the shift register.
The serial data into the DATA terminal are inputted to the shift register.
In this stage, the data in the latch is not changed.
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