MAX11041ETC+ Maxim Integrated Products, MAX11041ETC+ Datasheet - Page 12

• Manufacturer Part Number: MAX11041ETC+
• Description: IC REMOTE CTRLR WIRED 12-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX11041ETC+

• Applications: PDA's, Portable Audio/Video, Smartphones
• Interface: I²C
• Voltage - Supply: 1.6 V ~ 3.6 V
• Package / Case: 12-TQFN Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Wired Remote Controller
One data bit is transferred during each SCL clock cycle.
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is high and stable are considered control signals
(see the START and STOP Conditions section). Both
SDA and SCL remain high when the bus is not active.
The master initiates a transmission with a START condi-
tion, a high-to-low transition on SDA while SCL is high.
The master terminates a transmission with a STOP con-
dition, a low-to-high transition on SDA while SCL is high
(see Figure 7).
Data transfers are acknowledged with an acknowledge
bit (ACK) or a not-acknowledge bit (NACK). Both the
master and the MAX11041 generates ACK bits. To gen-
erate an ACK, pull SDA low before the rising edge of
the ninth clock pulse and keep it low during the high
period of the ninth clock pulse (see Figure 8). To gener-
ate a NACK, leave SDA high before the rising edge of
the ninth clock pulse and keep it high for the duration of
the ninth clock pulse. Monitoring NACK bits allows for
detection of unsuccessful data transfers. The master
can also use NACK bits to interrupt the current data
transfer to start another data transfer. If the master uses
NACK during a read from the FIFO, the FIFO word
pointer is not incremented and the next FIFO read pro-
duces the same FIFO word. Thus, the master must pro-
vide the ACK bit to advance the FIFO word pointer.
Table 4 shows the required resistor set for 30 key imple-
mentations. Resistors must have a 1% tolerance.
During jack insertion there may be several
false key entries written to the FIFO. When a jack inser-
tion/removal is detected, it is necessary to read the
FIFO repeatedly until the final change in jack state is
located (see Figure 9).
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Jack Insertion/Removal Detection
Applications Information
START and STOP Conditions
Required Resistor Set
Acknowledge Bits
Bit Transfer
In certain applications, a key triggers different events
depending on the duration of the keypress, simultane-
ous keypresses, or a specific order of keypresses.
In some applications, the duration of the keypress
determines the event triggered. For example, TALK
dials the entered phone number normally and initiates
voice dialing if it is held down. A second common use
of holding a key down is to generate a continuous
stream of events, such as the volume control or
fast forward.
Figure 9. Jack Insertion Detection
DETECTED
REMOVED
FALSE
JACK
JACK
KEYS
KEY TYPE
V
1. JACK INSERTION DETECTED AND ENTERED IN FIFO.
2. JACK REMOVAL DETECTED AND ENTERED IN FIFO.
3. JACK INSERTION DETECTED AND ENTERED IN FIFO.
4. FIFO IS READ UNTIL EMPTY (INT GOES HIGH).
INT
THE LAST READ BEFORE THE EMPTY FIFO IS REACHED
IS THE FINAL STATE OF THE JACK DETECTION.
➀
➁
➂
Extended Keypresses
Long Keypress Detection
➃
TIME
TIME