W83627DHG Nuvoton Technology Corporation of America, W83627DHG Datasheet - Page 148

• Manufacturer Part Number: W83627DHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627DHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11. UART PORT
11.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B)
The UARTs are used to convert parallel data into serial format for transmission and to convert serial
data into parallel format during reception. The serial data format is a start bit, followed by five to eight
data bits, a parity bit (if programmed) and one, one-and-a-half (five-bit format only) or two stop bits.
The UARTs are capable of handling divisors of 1 to 65535 and producing a 16x clock for driving the
internal transmitter logic. Provisions are also included to use this 16x clock to drive the receiver logic.
The UARTs also support the MIDI data rate. Furthermore, the UARTs also include a complete
modem control capability and 16-byte FIFOs for reception and transmission to reduce the number of
interrupts presented to the CPU.
11.2 Register Description
11.2.1 UART Control Register (UCR) (Read/Write)
The UART Control Register defines and controls the protocol for asynchronous data communication,
including data length, stop bit, parity, and baud rate selection.
Bit 7: BDLAB. When this bit is set to logical 1, designers can access the divisor (in 16-bit binary format)
Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is
Bit 5: PBFE. When PBE and PBFE of UCR are both set to logical 1,
Bit 4: EPE. When PBE is set to logical 1, this bit counts the number of logical 1's in the data word bits
Bit 3: PBE. When this bit is set to logical 1, the transmitter inserts a stop bit between the last data bit
from the divisor latches of the baud-rate generator during a read or write operation. When this bit
is set to logical 0, the Receiver Buffer Register, the Transmitter Buffer Register, and the Interrupt
Control Register can be accessed.
affected by this bit; the transmitter is not affected.
(1) if EPE is logical 1, the parity bit is fixed as logical 0 when transmitting and checking.
(2) if EPE is logical 0, the parity bit is fixed as logical 1 when transmitting and checking.
and determines the parity bit. When this bit is set to logical 1, the parity bit is set to logical 1 if an
even number of logical 1's are sent or checked. When the bit is set to logical 0, the parity bit is
logical 1 if an odd number of logic 1's are sent or checked.
and the stop bit of the SOUT, and the receiver checks the parity bit in the same position.
7
6
5
4
3
2
1
0
Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)
Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)
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Publication Release Date: Aug, 22, 2007
W83627DHG
Version 1.4