W83627UHG Nuvoton Technology Corporation of America, W83627UHG Datasheet - Page 155
W83627UHG
Manufacturer Part Number
W83627UHG
Description
IC I/O CONTROLLER 128-QFP
Manufacturer
Nuvoton Technology Corporation of America
Specifications of W83627UHG
Applications
PC's, PDA's
Interface
LPC
Voltage - Supply
3.3V, 5V
Package / Case
128-XFQFN
Mounting Type
Surface Mount
Pin Count
128
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Originally, the t2 timing is between 300 mS to 500 mS, but it can be changed to 200 mS to 300 mS by
programming Logical Device A, CR[E6h], bit 3 to “1”. Furthermore, the W83627UHG provides four
different extra delay time of PWROK for various demands. The four extra delay time are designed at
Logical Device A, CR[E6h], bits 2~1. The following table shows the definitions of Logical Device A,
CR[E6h] bits 3 ~1.
For example, if Logical Device A, CR[E6h] bit 2 is set to “0” and bits 2~1 are set to “10”, the range of t2
timing is from 396(300 + 96) mS to 596(500 + 96) mS.
NAME
V3
V4
V5
V6
t2
LOGICAL DEVICE A,
CR[E6H] BIT
5VCC Valid Voltage
5VCC Ineffective Voltage
3VCC Valid Voltage
3VCC Ineffective Voltage
Valid 5VCC and 3VCC to PWROK active
2~1
3
Table 13-4 Timing and the Voltage Parameters of PWROK
PARAMETER
PWROK_DEL (first stage) (VSB)
Set the delay time when rising from PWROK_LP to PWROK_ST.
0: 300 ~ 500 mS.
1: 200 ~ 300 mS.
PWROK_DEL (VSB)
Set the delay time when rising from PWROK_ST to PWROK.
00: No delay time.
10: 96 ms
-144-
DEFINITION
01: Delay 32 ms
11: Delay 250 ms
MIN.
300
2.6
2.1
-
-
W83627UHG
MAX.
500
4.3
2.9
-
UNIT
mS
V
V
V
V
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