Z8601720ASG Zilog, Z8601720ASG Datasheet - Page 73

• Manufacturer Part Number: Z8601720ASG
• Description: IC PCMCIA INTERFACE 100-VQFP
• Manufacturer: Zilog

Specifications of Z8601720ASG

• Applications: *
• Interface: *
• Voltage - Supply: *
• Package / Case: *
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

EEPROM Register
Address: SELECT 18h
Name: Window 3 Control Register
Type: Write/Read
Table 38.
Programming Internal Registers
Bit Placement
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bits 7-6
Window 3 Control Register: Address 18h
Bit Name
DIS_PAC3
EN_PAC3_MEM
EN_PAC3_16+
READ_PROTECT
EN_PAC3_ADDR_COMP
EN_PAC3_HCS
Z86017/Z16017 PCMCIA Interface Solution
Description
When set to 1, this bit disables Port 3 address control and
decoder.
When this bit is set to 1, Memory mode decoder is enabled.
When it is cleared, I/O mode decoder is enabled.
When this bit is set, data swapping is provided internal to
the chip during data reads from the low byte of the ATA
bus to the PCMCIA bus high byte, and from the high byte
of the PCMCIA bus to the low byte of the ATA bus during
data writes. When this bit is cleared, it is high byte to high
byte and low byte to low byte.
This bit allows two cards to be read from the same address.
When this bit is set, it prevents the PCMCIA bus from
becoming active.
When this bit is set, use address compare logic; when it is
cleared, acknowledge all PCMCIA chip selects.
When this bit is set, HCS1 is used as an external chip
select; when it is cleared, HCS0 is used as an external chip
select.
Number of wait states (in Master Clock periods) inserted
on the PCMCIA bus.
Product Specification
PS012002-1201
59